IMAGE DISPLAY UNIT AND METHOD FOR MANUFACUTRE THE SAME

• US 20080093602A1
• Filed: 10/19/2007
• Published: 04/24/2008
• Est. Priority Date: 10/20/2006
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Japan Display Incorporated
• Inventors: Hatano, Mutsuko, Sato, Takeshi, Toyota, Yoshiaki, Matsumura, Mieko
• Granted Patent: US 8,482,003 B2
• Time in Patent Office: Days
• US Class Current: 257/71
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

The present invention provides an image display unit, which can be manufactured in shorter time by designing a thin-film transistor, by which it is possible to reduce the number of processes of ion implantation and photolithographic processes. A gate electrode GT is designed in a laminated structure of a thin bottom layer metal film GMB and a top layer metal film GMT, and a top electrode of a storage capacitor Cst is designed to have only the bottom layer metal film GMB. Ion implanter for the bottom electrode of the storage capacitor Cst is passed through the thin bottom layer metal film GMB, and ion implantation is performed at the same time as the ion implantation of source-drain electrodes. The gate electrode of PMOSTFT has also only the bottom layer metal GMB, and the ion implantation for threshold adjustment is performed by using the same resist. By designing the thin-film transistor and the storage capacitor in such structure, one process each can be reduced in the photolithographic process and in the ion implantation process, and an active matrix substrate for an image display unit can be manufactured in shorter time and at lower cost.

Claims

1. An image display unit, comprising an active matrix substrate, which includes a plurality of gate lines deposited on an insulating substrate and a plurality of data lines prepared in matrix form on said plurality of gate lines, a plurality of pixels are deposited at intersections of said gate lines and said data lines and peripheral circuits including a driving circuit to drive said pixels are provided on outer side of a display region, which contains said plurality of pixels, there are provided a thin-film transistor and a storage capacitor on each of said pixels, and said active matrix substrate comprises a thin-film transistor on said peripheral circuit, wherein:

said gate line has a laminated structure including a bottom layer metal film and a top layer metal film, and a top electrode of said storage capacitor is a metal film on the same layer as said bottom layer metal film to make up said gate lines.

2. An image display unit according to claim 1, wherein said thin-film transistor is in two different types, i.e. n-channel conductive type and p-channel conductive type, a gate electrode of one of the thin-film transistors has a laminated structure with the same arrangement as said gate electrode, and a gate electrode of the other of the thin-film transistors is an electrode in the same layer as the bottom layer metal film of said gate electrode.

3. An image display unit according to claim 1, wherein said bottom layer metal film of said gate electrode is a transparent electrode.

4. An image display unit according to claim 1, wherein the film thickness of said bottom layer metal film is thinner than the film thickness of said top layer metal film.

5. An image display unit according to claim 4, wherein film thickness of said bottom layer metal film is in the range from 20 nm to 60 nm.

6. An image display unit according to claim 1, wherein the bottom electrode to make up the storage capacitor consists of the one with n-type polysilicon and the one with p-type polysilicon.

7. An image display unit according to claim 1, wherein the width of the bottom layer metal film to make up said gate electrode of said thin-film transistor is equal to the width of the top layer metal film.

8. An image display unit according to claim 1, wherein the width of the bottom layer metal film to make up said gate electrode of said thin-film transistor is wider than the width of the top layer metal film.

9. An image display unit according to claim 1, wherein the width of the bottom layer metal film to make up said gate electrode of said thin-film transistor in said peripheral circuit is wider than the width of the top layer metal film, and the width of the bottom layer metal film to make up said gate electrode of said thin-film transistor in said pixel is equal to the width of the top layer metal film.