High performance system-on-chip using post passivation process
First Claim
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1. An integrated circuit chip comprising:
- a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a pad, wherein said pad has a size between 0.5 and 30 micrometers;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, and wherein a first opening in said passivation layer exposes said pad, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;
a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers;
a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers.
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Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
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Citations
20 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a pad, wherein said pad has a size between 0.5 and 30 micrometers;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, and wherein a first opening in said passivation layer exposes said pad, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;
a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers;
a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit chip comprising:
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a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises an oxide layer and a nitride layer, wherein said nitride layer is over said oxide layer, and wherein a first opening in said passivation layer exposes a pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;
a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers; and
a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit chip comprising:
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a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises an oxide layer and a nitride layer, wherein said nitride layer is over said oxide layer, and wherein a first opening in said passivation layer exposes a pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;
a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers; and
a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification