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High performance system-on-chip using post passivation process

  • US 20080093745A1
  • Filed: 12/17/2007
  • Published: 04/24/2008
  • Est. Priority Date: 12/21/1998
  • Status: Abandoned Application
First Claim
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1. An integrated circuit chip comprising:

  • a silicon substrate;

    multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;

    a first dielectric layer over said silicon substrate;

    a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a pad, wherein said pad has a size between 0.5 and 30 micrometers;

    a second dielectric layer between said first and second metal layers;

    a passivation layer over said first metallization structure and over said first and second dielectric layers, and wherein a first opening in said passivation layer exposes said pad, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;

    a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers;

    a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers.

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