Deinterleaving Transpose Circuits in Digital Display Systems
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Abstract
The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the present invention converts the pixel data stream according to a predetermined output format. The apparatus of the present invention receives the pixel data in a “real-time” fashion, and dynamically performs predefined permutations so as to accomplish the predefined transpose operation. Alternatively, the pixel data are stored in a storage medium, and the apparatus of the present invention retrieves the pixel data and performs the predefined permutation to accomplish the predefined transpose operation. The methods and apparatus disclosed herein are especially useful for processing a high-speed stream of digital data in a flow-through manner and suitable for implementation in a hardware video pipeline. The control signal fanout and gate count of this invention are reduced compared to currently available similar techniques for converting pixel data into bitplane data.
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Citations
64 Claims
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1-26. -26. (canceled)
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27. A system comprising:
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a memory cell array, wherein a row of said array comprises a first and second subset, each subset having one or more memory cells;
a first wordline and a second wordline, wherein the first wordline is connected to the first subset memory cells, and the second wordline is connected to the second subset memory cells;
a first set of data to be loaded into the first subset of memory cells that are activated through the first wordline, wherein the first set of data is consecutively stored in a first region of a storage medium; and
a second set of data to be loaded into the second subset of memory cells that are activated through the second wordline, wherein the second set of data is consecutively stored in a second region of the storage medium. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A method for writing a memory cell array, wherein a row of the memory cell array comprises a first and second subset of memory cells, each subset having one or more memory cells, the method comprising:
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connecting the memory cells of the first subset to a first wordline, and the memory cells of the second subset to a second wordline;
storing a first and second set of data such that the data of the first set are stored consecutively in a first region and the data of the second set are consecutively stored in a second region separate from the first region;
activating the memory cells of the first subset through the first wordline; and
loading the first set of data into the activated first subset of memory cells. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
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64-96. -96. (canceled)
Specification