TEMPERATURE COMPENSATION OF SELECT GATES IN NON-VOLATILE MEMORY

• US 20080094930A1
• Filed: 12/18/2007
• Published: 04/24/2008
• Est. Priority Date: 06/16/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Dengtao Zhao, Nima Mokhlesi
• Inventors: Zhao, Dengtao, Mokhlesi, Nima
• Granted Patent: US 7,463,528 B2
• Time in Patent Office: Days
• US Class Current: 365/211
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

Claims

1. A method for operating non-volatile storage, comprising:

applying a first voltage to a selected word line to determine a programming condition of at least one non-volatile storage element which is associated with the selected word line, the at least one non-volatile storage element is provided in a set of non-volatile storage elements; and

applying a second voltage to a select gate associated with the at least one non-volatile storage element, during at least a portion of a time in which the first voltage is applied, a level of the second voltage is set based on a position of the at least one non-volatile storage element relative to the select gate.

2. The method of claim 1, wherein:

the second voltage is temperature-compensated when the at least one non-volatile storage element is not a direct neighbor of the select gate.

3. The method of claim 1, wherein:

the second voltage is not temperature-compensated when the at least one non-volatile storage element is a direct neighbor of the select gate.

4. The method of claim 1, wherein:

the second voltage is temperature-compensated by a first amount when the at least one non-volatile storage element is not a direct neighbor of the select gate; and

the second voltage is not temperature-compensated, or is temperature-compensated by an amount which is less than the first amount, when the at least one non-volatile storage element is a direct neighbor of the select gate.

5. The method of claim 1, wherein:

the first voltage comprises a read voltage for reading the programming condition of the at least one non-volatile storage element after the at least one non-volatile storage element has been programmed.

6. The method of claim 1, wherein:

the first voltage comprises a verify voltage for determining whether the at least one non-volatile storage element has reached a desired programming condition.

7. The method of claim 1, wherein:

the select gate and the at least one non-volatile storage element are in a NAND string.

8. The method of claim 7, wherein:

the select gate is at a source side of the NAND string.

9. The method of claim 7, wherein:

the select gate is at a drain side of the NAND string.

10. The method of claim 7, further comprising:

applying an additional voltage to an additional select gate in the NAND string during at least a portion of a time in which the first voltage is applied, the second voltage is temperature compensated and the additional voltage is not temperature-compensated or is temperature-compensated less than the second voltage.

11. A non-volatile storage system, comprising:

a set of non-volatile storage elements; and

one or more circuits in communication with the set of non-volatile storage elements via a plurality of word lines, the one or more circuits;

(a) apply a first voltage to a selected word line to determine a programming condition of at least one non-volatile storage element which is associated with the selected word line, the at least one non-volatile storage element is provided in the set of non-volatile storage elements, and (b) apply a second voltage to a select gate associated with the at least one non-volatile storage element, during at least a portion of a time in which the first voltage is applied, a level of the second voltage is set based on a position of the at least one non-volatile storage element relative to the select gate.

12. The non-volatile storage system of claim 11, wherein:

the second voltage is temperature-compensated when the at least one non-volatile storage element is not a direct neighbor of the select gate.

13. The non-volatile storage system of claim 11, wherein:

the second voltage is not temperature-compensated when the at least one non-volatile storage element is a direct neighbor of the select gate.

14. The non-volatile storage system of claim 11, wherein:

the second voltage is temperature-compensated by a first amount when the at least one non-volatile storage element is not a direct neighbor of the select gate; and

the second voltage is not temperature-compensated, or is temperature-compensated by an amount which is less than the first amount, when the at least one non-volatile storage element is a direct neighbor of the select gate.

15. The non-volatile storage system of claim 11, wherein:

the first voltage comprises a read voltage for reading the programming condition of the at least one non-volatile storage element after the at least one non-volatile storage element has been programmed.

16. The non-volatile storage system of claim 11, wherein:

the first voltage comprises a verify voltage for determining whether the at least one non-volatile storage element has reached a desired programming condition.

17. The non-volatile storage system of claim 11, wherein:

the select gate and the at least one non-volatile storage element are in a NAND string.

18. The non-volatile storage system of claim 17, wherein:

the select gate is at a source side of the NAND string.

19. The non-volatile storage system of claim 17, wherein:

the select gate is at a drain side of the NAND string.

20. The non-volatile storage system of claim 17, wherein:

the one or more circuits apply an additional voltage to an additional select gate in the NAND string during at least a portion of a time in which the first voltage is applied, the second voltage is temperature compensated and the additional voltage is not temperature-compensated or is temperature-compensated less than the second voltage.