Micro electro mechanical system

• US 20080096301A1
• Filed: 10/20/2006
• Published: 04/24/2008
• Est. Priority Date: 10/20/2006
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ramamoorthi, Sriram, Milligan, Donald J.
• Granted Patent: US 7,851,876 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2203/051 Translation according to an axis parallel to the substrate
• CPC Class Codes: B81B 2203/053 Translation according to an axis perpendicular to the substrate
• CPC Class Codes: B81C 1/00142 Bridges deformable micromirrors G02B26/0841
• CPC Class Codes: B81C 1/00253 Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/058 Aligning components using methods not provided for in B81C2203/051 - B81C2203/052
• CPC Class Codes: B81C 3/004 Active alignment, i.e. moving the elements in response to the detected position of the elements using internal or external actuators

Abstract

Embodiments of a micro electro mechanical system are disclosed.

Claims

1. A method of forming a micro-electro mechanical system (MEMS), comprising:

forming a first wafer, including removing material from said first wafer to define at least one flexure member and at least one proof mass;

forming a second wafer including an electronic circuit; and

bonding said first wafer to said second wafer, such that a gap is defined between said first wafer and said second wafer;

wherein a thickness of said at least one flexure member is independent of a thickness of said at least one proof mass.

2. The method of claim 1, wherein forming said first wafer comprises:

patterning a circuitry component on a first side of said first wafer;

removing material from said first side of said wafer to define a first side of said at least one flexure member; and

removing material from a second side of said first wafer to further define said at least one flexure member.

3. The method of claim 2, wherein removing material from said first side of said first wafer and said second side of said first wafer comprises etching, trenching, or micromachining said wafer.

4. The method of claim 1, wherein forming said first wafer includes forming at least one coupling block on said first wafer, wherein said coupling block is configured to couple at least a segment of said flexure to an anchoring portion of said first wafer.

5. The method of claim 1, further comprising sealing said MEMS with a protective unprocessed surface or wafer.

6. The method of claim 1, wherein bonding said first wafer to said second wafer comprises applying an adhesive between said first wafer and said second wafer.

7. The method of claim 1, wherein bonding said first wafer to said second wafer comprises optically aligning said first wafer to said second wafer through a window formed in said first wafer.

8. The method of claim 1, wherein said removing material from said first wafer to define at least one flexure member comprises removing a known amount of material to define a height and a width of said flexure to generate a desired spring constant of said flexure.

9. The method of claim 8, wherein said first wafer is configured to allow said proof mass to translate parallel to said second wafer.

10. The method of claim 8, wherein said first wafer is configured to allow said proof mass to translate perpendicular relative to said second wafer.

11. The method of claim 1, wherein said first wafer comprises a silicon on insulator (SOI) substrate.

12. The method of claim 1, further comprising:

defining a cavity with said first wafer, wherein said cavity is defined by subtracting a height of said proof mass from an original thickness of said first wafer; and

defining said cavity such that an x-y area of said cavity is larger than an x-y area of said proof mass.

13. A micro-electro mechanical system (MEMS) accelerometer, comprising:

a first wafer; and

a second wafer bonded to said first wafer;

wherein material is removed from at least a top surface and a bottom surface of said first wafer defining at least one flexure member and at least one proof mass;

wherein distribution of a proof mass of an x-y accelerometer and a z accelerometer on said first wafer are independently controllable.

14. The MEMS accelerometer of claim 13, wherein said first wafer defines a cavity on said top surface, wherein said cavity is defined by subtracting a height of said proof mass from an original thickness of said first wafer.

15. The MEMS accelerometer of claim 14, further comprising connecting said cavity to an external package volume through a deep trench.

16. The MEMS accelerometer of claim 13, wherein said first wafer comprises a window configured to allow for optical alignment of said first wafer with said second wafer.

17. The MEMS accelerometer of claim 13, wherein said first wafer comprises a silicon on insulator (SOI) wafer.

18. The MEMS accelerometer of claim 17, wherein:

a height of said at least one flexure member is defined by a height of a top silicon layer of said SOI wafer; and

a height of said proof mass is defined by a height said top silicon and a height of a processed handle wafer.

19. A MEMS transducer device, comprising:

a first wafer;

a second wafer, wherein material is removed from at least a top surface and a bottom surface of said second wafer defining at least one flexure member and at least one proof mass, wherein said first wafer is bonded to said second wafer;

at least one circuit operable to detect movement of said at least one flexure member;

wherein a sensitivity of said at least one circuit is independently controllable in an x-y plane and a z direction.

20. The MEMS transducer of claim 19, further comprising:

at least one via coupled to said first wafer;

said at least one via providing a path for electrical signals traveling through said first wafer.