PATTERNING OF DOPED POLY-SILICON GATES

• US 20080096372A1
• Filed: 10/22/2007
• Published: 04/24/2008
• Est. Priority Date: 10/23/2006
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Paraschiv, Vasile, Shamiryan, Denis, Demand, Marc
• Granted Patent: US 7,390,708 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers

Abstract

A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

Claims

1. A method for removing at least part of a deposited layer selectively over a substrate underneath, the deposited layer comprising at least one element which is not etchable, the method comprising the steps of:

depositing a layer comprising at least one element which is able to form at least one of a water-soluble chloride and a water-soluble bromide onto a substrate;

halogenating the element by exposing the deposited layer to a dry etch plasma comprising at least one halogen selected from the group consisting of chlorine and bromine;

removing the halogenated element using a water based wet etch step; and

performing a dry etch step to etch a remaining part of the deposited layer.

2. The method of claim 1, further comprising, after the step of depositing the layer, a step of doping the deposited layer to incorporate at least one element in the deposited layer.

3. The method of claim 2, wherein doping comprises ion implantation.

4. The method of claim 1, wherein the element is a Lanthanide element which is present in the deposited layer in a concentration of less than about 1% of a total composition of the deposited layer.

5. The method of claim 1, wherein removing the halogenated element comprises patterning of a structure, and wherein the method further comprises, after the step of depositing the layer, the step of:

depositing at least one photosensitive imaging layer and transferring the photolithographic pattern in the imaging layer to define a structure and to expose only parts of the deposited layer;

and further comprises, after the water based wet etch step, the steps of;

performing a dry etch step to etch a remaining part of the deposited layer to define a final structure; and

annealing the final structure such that the element is equally distributed into the final structure.

6. The method of claim 5, wherein removing the halogenated elements comprises patterning of a gate structure, wherein the deposited layer is a gate electrode layer, and wherein the method further comprises, before the step of depositing the gate electrode layer, the step of depositing a gate dielectric layer.

7. The method of claim 6, wherein the deposited layer is a poly-crystalline silicon layer for use as a gate electrode layer, and wherein the gate dielectric layer is comprises at least one layer selected from the group consisting of a high-k layer, a SiO₂ layer, and a SiON layer.

8. The method of claim 5, wherein the step of annealing is performed using a thermal anneal at 950°

C.

9. The method of claim 1, wherein the plasma comprises at least one of Cl₂ and BCl₃

10. The method of claim 1, wherein the plasma comprises at least one of HBr and Br₂.

11. The method of claim 6 further comprising, after the step of depositing a gate dielectric layer, the step of:

performing a dry etch step to etch the gate dielectric layer to complete a gate structure.

12. The method of claim 1, wherein the element is a Lanthanide selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.

13. The method of claim 1, wherein the element is Yb.

14. The method of claim 1, whereby the substrate is a silicon wafer.

15. Use of the method of claim 1 to fabricate a semiconductor device comprising a gate structure.