FLIP CHIP METALLIZATION METHOD AND DEVICES

• US 20080096379A1
• Filed: 12/01/2006
• Published: 04/24/2008
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: University of Utah (State of Utah)
• Inventors: Solzbacher, Florian, Harrison, Reid, Normann, Richard
• Granted Patent: US 7,388,288 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor

Abstract

Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wettable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.

Claims

1. A method of interconnect metallization for an electronic device having electrical contacts exposed through a passivation layer, comprising the steps of:

a) depositing an adhesion layer on the electrical contacts, the adhesion layer including titanium;

b) depositing a diffusion barrier layer on the adhesion layer, the diffusion barrier layer including platinum;

c) depositing a wettable layer on the diffusion barrier layer, the wettable layer including gold; and

d) depositing a wetting stop layer on a portion of the wettable layer, the wetting stop layer including titanium and tungsten.

2. The method of claim 1, wherein depositing the adhesion layer on the electrical contacts further comprises depositing the adhesion layer on a portion of the passivation layer.

3. The method of claim 1, further comprising the step of using photolithography to define features within at least one of the adhesion layer, diffusion barrier, wettable layer, and wetting stop layer.

4. The method of claim 3, further comprising the step of performing a lift off process to define features within at least one of the adhesion layer, diffusion barrier, wettable layer, and wetting stop layer.

5. The method of claim 1, further comprising the step of attaching solder bumps to an exposed portion of the wettable layer.

6. The method of claim 5, wherein attaching the solder bumps is performed by any of either screening a solder paste onto the wettable layer, attaching preformed solder bumps to the wettable layer, or electroplating solder bumps onto the wettable layer.

7. The method of claim 5, further comprising the step of soldering the electronic device to an integrated circuit to form an integrated neural probe, wherein the electronic device is an electrode array.

8. The method of claim 1, wherein the solder balls consist essentially of a mixture of 80% gold and 20% tin.

9. The method of claim 1, wherein the diffusion layer consists essentially of platinum.

10. The method of claim 1, wherein the wetting stop layer consists essentially of titanium and tungsten.

11. The method of claim 1, wherein the electronic device is an electrode array.

12. The method of claim 1, wherein the electronic device is an integrated circuit die.

13. A product produced by the method of claim 1.

14. A device compatible with flip chip bonding, comprising:

a) an electronic device having a plurality of electrical interconnects disposed in a planar array and exposed through a passivation layer; and

b) an underbump metallization stack disposed on at least one exposed electrical interconnect, the underbump metallization stack comprising;

i) an adhesion layer disposed on the electrical interconnect, the adhesion layer including titanium;

ii) a diffusion barrier disposed over the adhesion layer, the diffusion layer include platinum;

iii) a wettable layer disposed over the diffusion layer, the wettable layer including gold; and

iv) a wetting stop layer disposed over the wettable layer, the wetting stop layer including titanium and tungsten.

15. The device of claim 14, wherein the passivation layer comprises silicon nitride.

16. The device of claim 14, wherein:

the adhesion layer has a thickness of about 50 nanometers;

the diffusion barrier has a thickness of about 150 nanometers;

the wettable layer has a thickness of about 150 nanometers; and

the wetting stop layer has a thickness of about 100 nanometers.

17. The device of claim 14, wherein:

the adhesion layer consists essentially of titanium;

the diffusion layer consists essentially of platinum;

the wettable layer consists essentially of gold; and

the wetting stop layer consists essentially of titanium and tungsten.

18. The device of claim 14, wherein the diffusion layer consists essentially of platinum.

19. The device of claim 14 further comprising solder bumps attached to a portion of the wettable layer, the solder bumps consisting essentially of a mixture of 80% gold and 20% tin.

20. The device of claim 14, wherein the adhesion layer, diffusion barrier, and wettable layer define a plurality of octagonal shaped areas for attachment of solder bumps thereto.