Method for Producing Semiconductor Wafer and Semiconductor Wafer

• US 20080096474A1
• Filed: 10/12/2005
• Published: 04/24/2008
• Est. Priority Date: 10/27/2004
• Status: Active Grant

• Current Assignee: Shin-Etsu Handotai Co., Ltd. (Shin-Etsu Chemical Company Limited)
• Original Assignee: Shin-Etsu Handotai Co., Ltd. (Shin-Etsu Chemical Company Limited)
• Inventors: Kato, Tadahiro, Sekizawa, Masayoshi, Okada, Mamoru, Kijima, Hisashi
• Granted Patent: US 7,507,146 B2
• Time in Patent Office: Days
• US Class Current: 451/57
• CPC Class Codes: B24B 37/08 for double side lapping
• CPC Class Codes: B24B 9/065 of thin, brittle parts, e.g. semiconductors, wafers
• CPC Class Codes: H01L 21/02008 Multistep processes
• CPC Class Codes: H01L 21/02021 Edge treatment, chamfering

Abstract

The present invention is a method for producing a semiconductor wafer, comprising: at least a double-side polishing step; and a chamfered-portion polishing step; wherein as a first chamfered-portion polishing step, at least, a chamfered portion of the wafer is polished so that a chamfered surface of each of main surface sides in the chamfered portion is in contact with a polishing pad; then the double-side polishing is performed; as a second chamfered-portion polishing step, at least, the chamfered portion of the wafer is polished so that an end surface of the chamfered portion is in contact with a polishing pad and so that both main surfaces of the wafer are not in contact with a polishing pad. Thereby, when a semiconductor wafer is produced, scratch and such generated in the chamfered portion in a double-side polishing process can be removed and, excessive polishing in a peripheral portion of a main surface can be prevented from being caused in polishing a chamfered portion. Therefore, a method for producing a semiconductor wafer having a high flatness even in the vicinity of a chamfered portion, and the semiconductor wafer are provided.

Claims

1-8. -8. (canceled)

9. A method for producing a semiconductor wafer, comprising:

at least

a double-side polishing step; and

a chamfered-portion polishing step;

wherein as a first chamfered-portion polishing step, at least, a chamfered portion of the wafer is polished so that a chamfered surface of each of main surface sides in the chamfered portion is in contact with a polishing pad;

then

the double-side polishing is performed;

as a second chamfered-portion polishing step, at least, the chamfered portion of the wafer is polished so that an end surface of the chamfered portion is in contact with a polishing pad and so that both main surfaces of the wafer are not in contact with a polishing pad.

10. The method for producing a semiconductor wafer according to claim 9, wherein the semiconductor wafer is a silicon wafer.

11. The method for producing a semiconductor wafer according to claim 9, wherein in the first chamfered-portion polishing step, only the chamfered surface of each of main surface sides in the chamfered portion is polished.

12. The method for producing a semiconductor wafer according to claim 10, wherein in the first chamfered-portion polishing step, only the chamfered surface of each of main surface sides in the chamfered portion is polished.

13. The method for producing a semiconductor wafer according to claim 9, wherein in the second chamfered-portion polishing step, only the end surface of the chamfered portion is polished.

14. The method for producing a semiconductor wafer according to claim 10, wherein in the second chamfered-portion polishing step, only the end surface of the chamfered portion is polished.

15. The method for producing a semiconductor wafer according to claim 11, wherein in the second chamfered-portion polishing step, only the end surface of the chamfered portion is polished.

16. The method for producing a semiconductor wafer according to claim 12, wherein in the second chamfered-portion polishing step, only the end surface of the chamfered portion is polished.

17. The method for producing a semiconductor wafer according to claim 9, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

18. The method for producing a semiconductor wafer according to claim 10, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

19. The method for producing a semiconductor wafer according to claim 11, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

20. The method for producing a semiconductor wafer according to claim 12, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

21. The method for producing a semiconductor wafer according to claim 13, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

22. The method for producing a semiconductor wafer according to claim 14, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

23. The method for producing a semiconductor wafer according to claim 15, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

24. The method for producing a semiconductor wafer according to claim 16, wherein in the first chamfered-portion polishing step, the chamfered portion is polished so that the wafer is inclined at an angle in the range of 40-50°

with respect to a polishing surface of the polishing pad.

25. The method for producing a semiconductor wafer according to claim 9, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

26. The method for producing a semiconductor wafer according to claim 10, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

27. The method for producing a semiconductor wafer according to claim 11, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

28. The method for producing a semiconductor wafer according to claim 12, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

29. The method for producing a semiconductor wafer according to claim 13, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

30. The method for producing a semiconductor wafer according to claim 14, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

31. The method for producing a semiconductor wafer according to claim 15, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

32. The method for producing a semiconductor wafer according to claim 16, wherein in the second chamfered-portion polishing step, the chamfered portion is polished so that the wafer is perpendicular to a polishing surface of the polishing pad.

33. The method for producing a semiconductor wafer according to claim 9, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

34. The method for producing a semiconductor wafer according to claim 10, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

35. The method for producing a semiconductor wafer according to claim 11, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

36. The method for producing a semiconductor wafer according to claim 12, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

37. The method for producing a semiconductor wafer according to claim 13, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

38. The method for producing a semiconductor wafer according to claim 14, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

39. The method for producing a semiconductor wafer according to claim 15, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

40. The method for producing a semiconductor wafer according to claim 16, wherein the polishing pad used in the first chamfered-portion polishing step and the polishing pad used in the second chamfered-portion polishing step are different from each other.

41. A semiconductor wafer comprising, both surfaces and a chamfered portion that are polished, and a roll-off amount of 0.5 μ

m or less.