ITERATIVE MATRIX PROCESSOR BASED IMPLEMENTATION OF REAL-TIME MODEL PREDICTIVE CONTROL

• US 20080097625A1
• Filed: 10/22/2007
• Published: 04/24/2008
• Est. Priority Date: 10/20/2006
• Status: Active Grant

• Current Assignee: Lehigh University
• Original Assignee: Lehigh University
• Inventors: Kothare, Mayuresh V., Bleris, Leonidas, Arnold, Mark G., Vouzis, Panagiotis
• Granted Patent: US 7,844,352 B2
• Time in Patent Office: Days
• US Class Current: 700/29
• CPC Class Codes: G05B 13/048 using a predictor
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register

Abstract

A system for embedding real-time Model Predictive Control (MPC) in a System-on-a-Chip (SoC) devices is provided. In the system, a microprocessor is connected to an auxiliary unit or application-specific matrix coprocessor. The microprocessor can control the operation of the MPC algorithm, i.e., carry out the tasks of input/output for the MPC algorithm, initialize and send the appropriate commands to auxiliary unit and receive back the optimal control moves or instructions from auxiliary unit. The auxiliary unit can operate as a matrix coprocessor by executing matrix operations, e.g. addition, multiplication, inversion, etc., required by the MPC algorithm.

Claims

1. A system comprising:

a plant controlled by real-time model predictive control;

an iterative matrix processor configured to perform computations on vectors and matrices stored in a logarithmic format;

a general purpose processor in communication with the plant and the iterative matrix processor to transfer information between the plant and the iterative matrix processor, the general purpose processor being configured to issue a sequence of instructions to the iterative matrix processor to implement the model predictive control; and

wherein each instruction of the sequence of instructions initiates a series of element-by-element operations in the logarithmic format on scalars, vectors and matrices stored in the iterative matrix processor.

2. The system of claim 1 wherein:

the iterative matrix processor is configured to execute matrix by vector multiplication, scalar by vector multiplication, matrix-element zeroing, matrix-element negation, matrix-element reciprocal, vector-reciprocal square, vector-reciprocal cube, vector sum, vector multiply-accumulate, or matrix multiply-accumulate; and

the matrix-element reciprocal operation results in a negation in the logarithmic format, the vector-reciprocal square operation results in a shift and negation in the logarithmic format, the vector-reciprocal cube operation results in a shift, add and negation in the logarithmic format.

3. The system of claim 2 wherein the iterative matrix processor further comprises a pipelined logarithmic processor, the pipelined logarithmic processor is configured to execute matrix by vector multiplication, scalar by vector multiplication, vector sum, vector multiply-accumulate, matrix multiply-accumulate, matrix-element reciprocal, vector-reciprocal square, and vector-reciprocal cube.

4. The system of claim 3 wherein the iterative matrix processor delays computation with a later portion of a matrix while computing with an earlier portion of the matrix in response to a size of the matrix being small compared to a depth of the pipelined logarithmic processor.

5. The system of claim 4 wherein the computation delay is a predetermined number of clock cycles related to the depth of the pipelined logarithmic processor.

6. A controller to implement a real-time model predictive control algorithm, the controller comprising:

a microprocessor to execute a portion of the model predictive control algorithm; and

an iterative matrix processor configured to perform at least one matrix calculation of the model predictive control algorithm, and the iterative matrix processor being configured to operate using a logarithmic number system.

7. The controller of claim 6 wherein the iterative matrix processor is configured to execute a single multiply-accumulate operation at each clock cycle.

8. The controller of claim 6 wherein the iterative matrix processor is configured to execute multiple multiply-accumulate operations at each clock cycle.

9. The controller of claim 6 wherein the iterative matrix processor is configured to execute one-bit of a single multiply-accumulate operation at each clock cycle.

10. The controller of claim 6 wherein the iterative matrix processor is configured to execute at least one of matrix by vector multiplication, scalar by vector multiplication, matrix-element zeroing, matrix-element negation, matrix-element reciprocal, vector-reciprocal square, vector-reciprocal cube, vector sum, vector multiply-accumulate, or matrix multiply-accumulate.

11. A model predictive controller comprising:

a general purpose processor to execute a model predictive control algorithm;

an auxiliary unit in communication with the general purpose processor, the auxiliary unit being configured to execute at least one matrix calculation required by the model predictive control algorithm in response to receiving an instruction from the general purpose processor; and

wherein the auxiliary unit performs the at least one matrix calculation using a logarithmic number system.

12. The model predictive controller of claim 11 wherein the general purpose processor comprises a microprocessor, a memory device, at least one input/output connection and at least one bus interconnecting the microprocessor, the memory device and the at least one input/output connection.

13. The model predictive controller of claim 11 wherein the auxiliary unit comprises a control unit, a plurality of data memory units and a logarithmic number unit.

14. The model predictive controller of claim 13 wherein the control unit is a finite state machine.

15. The model predictive controller of claim 13 wherein the logarithmic number unit is a pipelined arithmetic logic unit.

16. The model predictive controller of claim 11 wherein the general purpose processor and the auxiliary unit are configured to operate using a 16-bit word length.

17. The model predictive controller of claim 11 wherein the general purpose processor provides the auxiliary unit with required matrices for optimizing the model predictive control algorithm at a start of the model predictive control algorithm, and the auxiliary unit stores the required matrices for later use in optimizing the model predictive control algorithm.

18. The model predictive controller of claim 17 wherein the general purpose processor provides the auxiliary unit with a sequence of commands to optimize the model predictive algorithm and the auxiliary unit provides the general purpose processor with a control command.