LOAD BALANCING FOR A SYSTEM OF CRYPTOGRAPHIC PROCESSORS

• US 20080098233A1
• Filed: 10/20/2006
• Published: 04/24/2008
• Est. Priority Date: 10/20/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sutter, Siegfried K.H., Fayad, Camil, Dewkett, Thomas J., Li, John K., Yeh, Phil C.
• Granted Patent: US 7,870,395 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.

Claims

1. A method for controlling cryptographic operations in a plurality of cryptographic processors, said method comprising the steps of:

providing a plurality of instruction streams from a memory;

supplying said instruction streams to said processors initially based on location within said memory; and

retrieving subsequent instruction streams by said processors from dynamically partitioned locations in said memory assigned.

2. A method for controlling cryptographic operations comprising the step of supplying a balanced set of instruction streams from memory to a plurality of distinct cryptographic processors operating securely and in a coordinated fashion.

3. A method for controlling cryptographic operations comprising the step of supplying a balanced set of instruction streams from memory to an array of groups of cryptographic processors with the processors in each group operating securely and in a coordinated fashion.

4. The method of claim 3 in which said at least one of said cryptographic processors include a cryptographic engine capable of processing requests in a pipelined fashion.

5. The method of claim 3 in which each cryptographic processor includes a cryptographic engine, a microprocessor for controlling said engine, an interface for supplying instructions to said processor and a switch for controlling the flow of information amongst said engine, said microprocessor and said interface.

6. A system for carrying out cryptographic operations, said system comprising:

an array of groups of processors, with each of said groups including a plurality of cryptographic processors operating together and in a secure fashion; and

a source of instructions matched to the capacities of the cryptographic processors to which they are directed.

7. The system of claim 6 in which said source of instructions includes a dynamically partioned memory.

8. The system of claim 6 in which at least one of said cryptographic processors includes a cryptographic engine capable of processing requests in a pipelined fashion.

9. The system of claim 6 in which all of said cryptographic processors include a cryptographic engine capable of processing requests in a pipelined fashion.