Method of timing calibration using slower data rate pattern
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Accused Products
Abstract
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
29 Citations
195 Claims
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1-186. -186. (canceled)
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187. An apparatus comprising:
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a receiving circuit for receiving a calibration bit pattern at a digital circuit, the digital circuit also receiving incoming data;
a memory device for storing the received calibration bit pattern; and
an adjusting circuit for using the stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of the digital circuit to produce a reliable detection of the calibration bit pattern, wherein the receiving circuit receives the calibration bit pattern at a first data rate which is lower than a data rate at which the digital circuit receives incoming data. - View Dependent Claims (188, 189, 190, 191, 192, 193, 194, 195)
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Specification