Integrated matching network and method for manufacturing integrated matching networks

• US 20080099800A1
• Filed: 10/25/2006
• Published: 05/01/2008
• Est. Priority Date: 10/25/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Miller, Melvy F., Foerstner, Juergen A.
• Granted Patent: US 7,528,062 B2
• Time in Patent Office: Days
• US Class Current: 257/276
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (101), a second die having a capacitor (102), and a metal interconnect (108) coupled to the PA and the first capacitor. The metal interconnect (108) has an inductance. The capacitor (102) and metal interconnect (108) form a shunt impedance.

Claims

1. A method for manufacturing an integrated matching network, the method comprising the steps of:

coupling a first die to a substrate, the first die having first and second opposing surfaces, the first surface of the first die coupled to the substrate;

coupling a second die to the substrate, the second die having first and second opposing surfaces and a capacitance, the first surface of the second die coupled to the substrate; and

coupling a first metallization layer to the second surface of the first die and the second surface of the second die, the first metallization layer having an inductance, the capacitance and the inductance together providing a shunt impedance from the first die to the substrate.

2. A method according to claim 1, wherein said step of coupling a first die comprises forming an RF active component on the substrate;

and wherein said step of forming a second die comprises forming a capacitor on the substrate.

3. A method according to claim 1, wherein said step of coupling a first metallization layer comprises:

coupling the second surface of the first die to the first metallization layer with a first bump attachment; and

coupling the second die to the first metallization layer with a second bump attachment.

4. A method according to claim 1 further comprising:

coupling a third die on the substrate; and

coupling the third die to the first die with a second metallization layer.

5. A method according to claim 4, wherein said step of coupling the third die to the first die comprises:

coupling the first metallization layer to the second metallization layer with a first via; and

coupling the third die to the second metallization layer with a second via.

6. A method according to claim 1 further comprising:

coupling a third die to the substrate;

forming the first metallization layer on an insulator layer;

forming first and second vias through the insulator layer; and

forming a second metallization layer on the insulator layer, the first via coupling the second metallization layer to the first metallization layer, the second via coupling the second metallization layer to the third die.

7. A method for manufacturing a radio frequency (RF) device having an integrated matching network, the method comprising the steps of:

coupling an RF active die to a first substrate, the RF active die having first and second opposing surfaces, the first surface of the RF active die coupled to the first substrate;

coupling a first integrated passive device (IPD) to the first substrate, the first IPD having first and second opposing surfaces and a first capacitance incorporated therewith, the first surface of the first IPD coupled to the first substrate; and

coupling a second substrate on the second surface of the die and the second surface of the first IPD, the second substrate having an inductance.

8. A method according to claim 7, wherein the RF device has an output and an RF ground;

and wherein the first capacitance and the inductance together provide a shunt impedance from the output of the RF device to the RF ground.

9. A method according to claim 7, wherein said step of coupling a second substrate comprises coupling a metal interconnect to the first surface of the RF active die and the first surface of the first IPD, the metal interconnect having the inductance.

10. A method according to claim 7, wherein said step of coupling a second substrate comprises:

applying a first bump attachment to the second surface of the RF active die;

applying a second bump attachment to the second surface of the first IPD; and

coupling a metal interconnect to the first and second bump attachments.

11. A method according to claim 7, wherein said step of coupling a second substrate comprises:

forming a first contact on the second surface of the RF active die;

applying a first bump attachment to the first contact;

forming a second contact on the second surface of the first IPD;

applying a second bump attachment to the second contact; and

coupling a metal interconnect to the first and second bump attachments.

12. A method according to claim 7 further comprising coupling a second IPD to the first substrate, the second IPD having first and second opposing surfaces;

and

wherein said step of coupling a second substrate comprises coupling the second substrate to the second surface of the RF active die, the second surface of the first IPD, and the second surface of the second IPD.

13. A method according to claim 7 further comprising coupling a second IPD to the first substrate, the second IPD having first and second opposing surfaces, the first surface of the second IPD coupled to the first substrate;

and wherein said step of coupling a second substrate comprises;

applying a first bump attachment to the second surface of the RF active die;

applying a second bump attachment to the second surface of the first IPD;

coupling a first metal interconnect to the first and second bump attachments;

applying a third bump attachment to the second surface of the second IPD; and

coupling a second metal interconnect to the first bump attachment and the third bump attachment.

14. A method according to claim 13, wherein the RF device has an RF ground;

wherein the first metal interconnect has a first inductance and the second metal interconnect has a second inductance;

wherein the first inductance and the first capacitance form a shunt impedance to the RF ground;

wherein the second IPD has a second capacitance coupled to the shunt impedance to the RF ground; and

wherein the second inductance and the second capacitance coupled to the shunt impedance to the RF ground together form an output impedance matching network.

15. A method according to claim 7 further comprising coupling a second IPD to the first substrate, the second IPD having first and second opposing surfaces, the first surface of the second IPD coupled to the first substrate;

and wherein said step of coupling a second substrate comprises;

forming a first metallization layer on an insulator substrate;

forming first and second vias through the insulator substrate;

forming a second metallization layer on the insulator substrate, the second metallization layer coupled to the first metallization layer with the first via;

coupling the second metallization layer to the second surface of the RF active die and the second surface of the first IPD while coupling the first metallization layer to the second surface of the second IPD with the second via.

16. An integrated matching network comprising:

a first die comprising an RF active component;

a second die comprising first capacitor; and

a first metal interconnect coupled to said RF active component and said first capacitor, said first metal interconnect having a first inductance, said first capacitor and said first inductance forming a shunt impedance.

17. An integrated matching network according to claim 16 further comprising:

a first bump attachment coupled to said RF active component;

a second bump attachment coupled to said first capacitor; and

wherein said metal interconnect is coupled to said first and second bump attachments, wherein said RF active component comprises a power amplifier, and wherein said first capacitor is an integrated passive device.

18. An integrated matching network according to claim 16 further comprising:

a third die comprising a second capacitor coupled to said shunt impedance; and

a second metal interconnect coupled to said first metal interconnect and said second capacitor, said second metal interconnect having a second inductance, said second inductance and said second capacitor coupled to said shunt impedance forming an output impedance matching network.

19. An integrated matching network according to claim 16 further comprising an inductor component coupled to said first and second dies, said inductor component comprising:

a first contact coupled to said RF active component;

a second contact coupled to said first capacitor;

a first bump attachment coupled to said first contact; and

a second bump attachment coupled to said second contact;

wherein said first metal interconnect is coupled to said first and second bump attachments.

20. An integrated matching network according to claim 16, wherein said first metal interconnect has first and second opposing surfaces;

and wherein the integrated matching network further comprises;

a third die comprising a second capacitor;

an inductor component coupled to said first, second, and third dies, said inductor component comprising;

an insulating layer having first and second opposing surfaces and first and second vias, said first surface of said insulating layer coupled to said second surface of said first metal interconnect; and

a second metal interconnect coupled to said second surface of said insulating layer, said first via coupling said second metal interconnect to said second surface of said first metal interconnect;

a first bump attachment coupled to said RF active component;

a second bump attachment coupled to said first capacitor, said first surface of said first metal interconnect coupled to said first and second bump attachments; and

a third bump attachment coupled to said second capacitor, said second via coupling said second metal interconnect to said third bump attachment.