MEMORY CELL AND METHOD FOR FORMING THE SAME

• US 20080099816A1
• Filed: 01/02/2008
• Published: 05/01/2008
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Kris Brown
• Inventors: Brown, Kris
• Granted Patent: US 7,518,174 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor memory cell structure having 4F² dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Claims

1-100. -100. (canceled)

101. A memory cell formed on a surface of a substrate, comprising:

a vertical transistor comprising;

an active region formed in the substrate;

an epitaxial post extending from the surface of the substrate over the active region; and

a gate formed at least partially around a perimeter of the epitaxial post; and

a memory cell capacitor formed over the epitaxial post.

102. The memory cell of claim 101 wherein the epitaxial post comprises a lightly doped conductive region formed therein to electrically couple the memory cell capacitor to the epitaxial post of the vertical transistor.

103. The memory cell of claim 101 wherein the memory cell capacitor comprises a container-shaped capacitor structure.

104. The memory cell of claim 101 wherein the memory cell capacitor comprises a stacked capacitor structure.

105. The memory cell of claim 101 wherein the memory cell capacitor comprises a finned capacitor structure.

106. The memory cell of claim 101 wherein the epitaxial post comprises a generally quadrilateral cross-sectional area.

107. The memory cell of claim 101 wherein the epitaxial post comprises a generally circular cross-sectional area.

108. The memory cell of claim 101 wherein the epitaxial post comprises a generally polygonal cross-sectional area.

109. A memory cell formed on a surface of a substrate, comprising:

an active region formed in the substrate;

a vertical transistor at least partially formed in a semiconductor post, the semiconductor post formed on the surface of the substrate and extending therefrom, the vertical transistor further having a gate formed at least partially around a perimeter of the semiconductor post; and

a memory cell capacitor electrically coupled to the semiconductor post of the vertical transistor.

110. The memory cell of claim 109 wherein the active region comprises a highly doped region to promote conductivity to a digit line contact.

111. The memory cell of claim 109 wherein the memory cell shares at least one digit contact with an adjacent memory cell, and wherein the digit contact is offset in relation to the semiconductor posts of the memory cell and the adjacent memory cell.

112. The memory cell of claim 109 wherein the memory cell capacitor comprises a container-shaped capacitor structure.

113. The memory cell of claim 109 wherein the memory cell capacitor comprises a stacked capacitor structure.

114. The memory cell of claim 109 wherein the memory cell capacitor comprises a finned capacitor structure.

115. The memory cell of claim 109 wherein the epitaxial post comprises a generally quadrilateral cross-sectional area.

116. The memory cell of claim 109 wherein the epitaxial post comprises a generally circular cross-sectional area.

117. The memory cell of claim 109 wherein the epitaxial post comprises a generally polygonal cross-sectional area.

118. A plurality of memory cells formed on a surface of a substrate, comprising:

an active region formed in the substrate;

a plurality of semiconductor posts formed on the surface of the substrate over the active region;

a plurality of memory cell capacitors each formed over a respective one of the plurality of semiconductor posts; and

a plurality of gate structures each formed adjacent a respective one of the plurality of semiconductor posts to provide a respective vertical transistor configured to electrically couple a respective one of the memory cell capacitors to the active region.

119. The plurality of memory cells of claim 118, further comprising an isolation region formed adjacent the active region.

120. The plurality of memory cells of claim 118, further comprising a digit contact electrically coupled to the active region.

121. The plurality of memory cells of claim 120 wherein the digit contact comprises a digit contact disposed between first and second adjacent semiconductor posts, the digit contact offset in relation to the first and second adjacent semiconductor posts.

122. The plurality of memory cells of claim 120 wherein the digit contact comprises a digit contact disposed between first and second adjacent semiconductor posts and having a portion extending into a region between the first and second adjacent semiconductor posts.

123. The plurality of memory cells of claim 120, further comprising a digit line coupled to the digit contact.

124. The plurality of memory cell of claim 120 wherein the active region comprises a highly doped region to promote conductivity to the digit contact.

125. The plurality of memory cells of claim 118, further comprising a plurality of digit lines each formed in the substrate and electrically coupled to at least one of the semiconductor posts.