Nonvolatile memory devices and methods of fabricating the same

• US 20080099822A1
• Filed: 12/07/2006
• Published: 05/01/2008
• Est. Priority Date: 11/01/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Hyun-sug, Park, Se-jong, Yang, Bong-gil, Uom, Jung-sup, Ju, Sup-youl
• Granted Patent: US 7,915,118 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

A nonvolatile memory device may include a semiconductor substrate, a floating gate electrode on the semiconductor substrate that includes an acute-angled tip at an upper end, and a control gate electrode insulated from the floating gate electrode and facing at least a portion of the floating gate electrode, wherein an angle formed between the semiconductor substrate and an upper portion of a lateral surface of the floating gate electrode is smaller than an angle formed between the semiconductor substrate and a lower portion of the lateral surface of the floating gate electrode

Claims

1. A nonvolatile memory device, comprising:

a semiconductor substrate;

a floating gate electrode on the semiconductor substrate, and including an acute-angled tip at an upper end; and

a control gate electrode insulated from the floating gate electrode and facing at least a portion of the floating gate electrode,

wherein an angle formed between the semiconductor substrate and an upper portion of a lateral surface of the floating gate electrode is smaller than an angle formed between the semiconductor substrate and a lower portion of the lateral surface of the floating gate electrode.

2. The nonvolatile memory device as claimed in claim 1, wherein the lower portion of the lateral surface of the floating gate electrode is recessed inward with respect to the acute-angled tip.

3. The nonvolatile memory device as claimed in claim 1, wherein:

the lateral surface of the floating gate electrode has a concave curved shape; and

a radius of curvature of the upper portion of the lateral surface is smaller than a radius of curvature of the lower portion of the lateral surface.

4. The nonvolatile memory device as claimed in claim 1, wherein the lateral surface of the floating gate electrode includes a concave curved section at the upper portion thereof and a straight section at the lower portion thereof.

5. The nonvolatile memory device as claimed in claim 1, wherein the lateral surface of the floating gate electrode includes a straight section at the upper portion thereof and a concave curved section at the lower portion thereof.

6. The nonvolatile memory device as claimed in claim 1, wherein the lateral surface of the floating gate electrode includes a first straight section at the upper portion thereof and a second straight section at the lower portion thereof.

7. The nonvolatile memory device as claimed in claim 1, wherein an angle formed between the semiconductor substrate and the lower portion of the lateral surface of the floating gate electrode is about 90°

.

8. The nonvolatile memory device as claimed in claim 1, wherein the control gate electrode at least partially overlaps an upper surface of the floating gate electrode and the lateral surface of the floating gate electrode.

9. The nonvolatile memory device as claimed in claim 8, further comprising:

a first gate insulating film interposed between the semiconductor substrate and the control gate electrode and between the semiconductor substrate and the floating gate electrode;

a second gate insulating film interposed between the lateral surface of the floating gate electrode and the control gate electrode; and

an isolation oxide film covering the upper surface of the floating gate electrode.

10. A method of fabricating a nonvolatile memory device, the method comprising:

forming a floating gate electrode on a semiconductor substrate, the floating gate electrode including an acute-angled tip at an upper end; and

forming a control gate electrode insulated from the floating gate electrode, and facing at least a portion of the floating gate electrode,

wherein an angle formed between the semiconductor substrate and an upper portion of a lateral surface of the floating gate electrode is smaller than an angle formed between the semiconductor substrate and a lower portion of the lateral surface of the floating gate electrode.

11. The method as claimed in claim 10, wherein the lower portion of the lateral surface of the floating gate electrode is recessed inward with respect to the acute-angled tip.

12. The method as claimed in claim 10, wherein forming the floating gate electrode comprises:

forming a sacrificial film having an opening on the semiconductor substrate;

forming a sacrificial spacer on a side of the opening;

forming a floating gate conductive film inside the opening where the sacrificial spacer is formed; and

removing the sacrificial film and the sacrificial spacer.

13. The method as claimed in claim 12, wherein:

a lateral surface of the sacrificial spacer is formed in a convex curved shape, and a radius of curvature of an upper portion of the lateral surface of the sacrificial spacer is smaller than a radius of curvature of a lower portion of the lateral surface thereof; and

the lateral surface of the floating gate electrode is formed in a concave curved shape, and a radius of curvature of the upper portion of the lateral surface of the floating gate electrode is smaller than a radius of curvature of the lower portion of the lateral surface of the floating gate electrode.

14. The method as claimed in claim 12, wherein:

a lateral surface of the sacrificial spacer includes a convex curved section at the upper portion thereof and a straight section at the lower portion thereof; and

the lateral surface of the floating gate electrode includes a concave curved section at the upper portion thereof and a straight section at the lower portion thereof.

15. The method as claimed in claim 12, wherein:

an angle formed between the semiconductor substrate and the lower portion of a lateral surface of the sacrificial spacer is about 90°

; and

an angle formed between the semiconductor substrate and the lower portion of the lateral surface of the floating gate electrode is about 90°

.

16. The method as claimed in claim 12, further comprising forming a mask film through which the opening is exposed on the sacrificial film, wherein the mask film on the sacrificial film is removed during the formation of the floating gate conductive film.

17. The method as claimed in claim 16, wherein:

the sacrificial spacer includes a silicon nitride film; and

the mask film includes polysilicon.

18. The method as claimed in claim 12, further comprising oxidizing an upper surface of the floating gate conductive film formed inside the opening.

19. The method as claimed in claim 18, further comprising:

forming a first gate insulating film on the semiconductor substrate before forming the floating gate electrode; and

forming a second gate insulating film on an exposed lateral surface of the floating gate electrode after forming the floating gate electrode.

20. The method as claimed in claim 12, wherein removing the sacrificial film and the sacrificial spacer comprises performing a wet etching method.