Manufacturing method of semiconductor device and semiconductor device

• US 20080099876A1
• Filed: 10/05/2007
• Published: 05/01/2008
• Est. Priority Date: 10/27/2006
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Seto, Masaru
• Granted Patent: US 7,867,890 B2
• Time in Patent Office: Days
• US Class Current: 257/522
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

The present invention provides a method of manufacturing a semiconductor device, which comprises steps of forming a plurality of wirings on a first insulting film formed on a semiconductor substrate so as to adjoin one another, forming a second insulating film on the first insulating film by a plasma CVD method and covering the wirings with the second insulating film in such a manner that air gaps are formed between the respective adjacent wirings, forming a third insulating film on the second insulating film by a high density plasma CVD method, and forming a fourth insulating film high in moisture resistance on the third insulating film.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps of:

forming a plurality of wirings over a first insulting film formed over a semiconductor substrate so as to adjoin one another;

forming a second insulating film over the first insulating film by a plasma CVD method and covering the wirings with the second insulating film in such a manner that air gaps are formed between the respective adjacent wirings;

forming a third insulating film over the second insulating film by a high density plasma CVD method; and

forming a fourth insulating film higher in moisture resistance than the second and third insulating films over the third insulating film.

2. The method according to claim 1, wherein a multilayered wiring layer is formed over the semiconductor substrate, and the wirings are part of the multilayered wiring layer and wirings each corresponding to a top layer of the multilayered wiring layer.

3. The method according to claim 1, wherein the second insulating film is a silicon oxide film.

4. The method according to claim 1, wherein the thickness of the second insulting film is 3000 Å

or more.

5. The method according to claim 1, wherein the third insulating film is a silicon oxide film.

6. The method according to claim 1, wherein the fourth insulating film is a silicon nitride film.

7. The method according to claim 1, wherein the semiconductor device is a semiconductor memory device and includes at least one memory cell and bit lines each of which reads data from the memory cell, and

wherein the wirings correspond to the bit lines.

8. The method according claim 1, wherein the semiconductor device is a semiconductor memory device and the semiconductor substrate includes a memory cell area in which at least one memory cell is formed, and a peripheral area in which at least one peripheral transistor is formed, and

wherein the air gaps are formed between the adjacent wirings disposed over the memory cell area.

17. The method according to claim 2, wherein the second insulating film is a silicon oxide film.

18. The method according to claim 2, wherein the thickness of the second insulting film is 3000 Å

or more.

19. The method according to claim 3, wherein the thickness of the second insulting film is 3000 Å

or more.

20. The method according to claim 17, wherein the thickness of the second insulting film is 3000 Å

or more.

9. A semiconductor device comprising:

a semiconductor substrate;

a first insulating film formed over the semiconductor substrate;

a plurality of wirings formed over the first insulating film so as to adjoin one another;

a second insulating film which is formed over the first insulating film by a CVD method and covers the wirings in such a manner that air gaps are formed between the adjacent wirings;

a third insulating film formed over the second insulating film by a high density plasma CVD method; and

a fourth insulating film formed over the third insulating film and higher in moisture resistance than the second and third insulating films.

10. The semiconductor device according to claim 9, wherein a multilayered wiring layer is formed over the semiconductor substrate, and the wirings are part of the multilayered wiring layer and wirings each corresponding to a top layer of the multilayered wiring layer.

11. The semiconductor device according to claim 9, wherein the second insulating film is a silicon oxide film.

12. The semiconductor device according to claim 9, wherein the thickness of the second insulting film is 3000 Å

or more.

13. The semiconductor device according to claim 9, wherein the third insulating film is a silicon oxide film.

14. The semiconductor device according to claim 9, wherein the fourth insulating film is a silicon nitride film.

15. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor memory device and includes at least one memory cell and bit lines each of which reads data from the memory cell, and

wherein the wirings correspond to the bit lines.

16. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor memory device and the semiconductor substrate includes a memory cell area in which at least one memory cell is formed, and a peripheral area in which at least one peripheral transistor is formed, and

wherein the air gaps are formed between the adjacent wirings disposed over the memory cell area.