PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES

• US 20080099917A1
• Filed: 12/26/2007
• Published: 05/01/2008
• Est. Priority Date: 04/22/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brooks, J., Jiang, Tongbi
• Granted Patent: US 7,550,847 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Claims

1-74. -74. (canceled)

75. A packaged semiconductor device, comprising:

a substrate having a substrate surface and a recess extending from the substrate surface into the substrate;

a semiconductor die in the recess, the semiconductor die having an integrated circuit and a bond site proximate to the substrate surface;

an electric coupler on the bond site of the semiconductor die;

a dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess of the substrate, the first portion of the dielectric layer having a thickness approximately equal to a height of the electric coupler relative to the substrate surface; and

a conductive link on the dielectric layer and in direct contact with the electric coupler.

76. The packaged semiconductor device of claim 75 wherein the substrate comprises a thermally conductive substrate.

77. The packaged semiconductor device of claim 75 wherein the substrate comprises at least one of copper and aluminum.

78. The packaged semiconductor device of claim 75 wherein:

the substrate has a first coefficient of thermal expansion; and

the semiconductor die has a second coefficient of thermal expansion at least approximately equal to the first coefficient of thermal expansion.

79. The packaged semiconductor device of claim 75 wherein the substrate has a first coefficient of thermal expansion that is approximately equal to a second coefficient of thermal expansion of a printed circuit board.

80. The packaged semiconductor device of claim 75 wherein the dielectric layer is a first dielectric layer, and wherein the packaged semiconductor device further comprises:

a second dielectric layer on the conductive link and the first dielectric layer, the second dielectric layer having a via proximate to the conductive link;

a ball site at least partially in the via; and

a solder ball on the ball site.

81. A packaged semiconductor device, comprising:

a substrate having a substrate surface and a recess extending from the substrate surface into the substrate;

a semiconductor die in the recess and having an integrated circuit and a bond site proximate to the substrate surface;

an electric coupler having a first end contacting the bond site of the semiconductor die and a second end opposite the first end;

a dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite the first surface, wherein the second end of the electric coupler does not project beyond the second surface of the dielectric layer; and

a conductive link on the second surface of the dielectric layer and in electrical communication with the electric coupler.

82. The packaged semiconductor device of claim 81 wherein the recess has a recess height and the semiconductor die has a die height less than the recess height.

83. The packaged semiconductor device of claim 81 wherein the second portion of the dielectric material fills a gap in the recess between the substrate and the semiconductor die.

84. The packaged semiconductor device of claim 81 wherein the electric coupler has a height between the first end and the second end, and wherein the height of the electric coupler is approximately equal to a distance between the first and second surfaces of the dielectric layer.

85. The packaged semiconductor device of claim 81 wherein the dielectric layer is a first dielectric layer, and wherein the packaged semiconductor device further comprises:

a second dielectric layer on the conductive link and the second surface of the first dielectric layer, the second dielectric layer having a via generally aligned with the conductive link; and

a ball site in the via and in electrical communication with the conductive link.

86. The packaged semiconductor device of claim 85 wherein the conductive link having a first end proximate to the electric coupler and a second end extending laterally on the second surface of the first dielectric layer from the first end, and wherein the via is generally aligned with the second end of the conductive link.

87. The packaged semiconductor device of claim 85 wherein the conductive link having a first end proximate to the electric coupler and a second end extending laterally on the second surface of the first dielectric layer from the first end, and wherein the first end of the conductive link is in physical contact with the second end of the electric coupler.

88. A packaged semiconductor device, comprising:

a substrate having a substrate surface and a recess extending from the substrate surface into the substrate;

a semiconductor die in the recess and having a first side with a bond site and a second side opposite the first side; and

a redistribution assembly coupled to the substrate, the redistribution assembly having an electric coupler on the bond site of the semiconductor die, a dielectric layer having a first portion over the first side of the semiconductor die and the electric coupler and a second portion in the recess, and a conductive link on the dielectric layer and in physical contact with the electric coupler.

89. The packaged semiconductor device of claim 88 wherein the electric coupler having a first end on the bond site of the semiconductor die and a second end opposite the first end, and wherein the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite to the first surface, and wherein the second surface of the dielectric layer is generally transversely aligned with the second end of the electric coupler.

90. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site in electrical communication with the semiconductor die.

91. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site generally aligned with the conductive link.

92. The packaged semiconductor device of claim 91 wherein the dielectric layer is a first dielectric layer, and wherein the redistribution assembly further comprises a second dielectric layer on the conductive link and the first dielectric layer, and wherein the second dielectric layer includes a via containing the ball site.

93. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site in electrical communication with the semiconductor die and a solder ball on the ball site.