HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
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Accused Products
Abstract
The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
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Citations
317 Claims
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1-289. -289. (canceled)
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290. A structure, comprising:
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a first space transformer having a first surface, a second surface, a plurality of contact locations disposed on the second surface thereof, and a plurality of elongated electrical conductors connected to the first surface thereof, said first space transformer adapted in use such that ends of the plurality of elongated electrical conductors for making pressure contacts with a corresponding plurality of contact locations on a semiconductor wafer; and
an interconnection structure having a first surface, a second surface, a first plurality of electrical conductors extending from the first surface thereof, said electrical interconnection structure adapted in use such that contact regions of the first plurality of electrical conductors make pressure connections with the plurality of contact locations on the second surface of the first space transformer, the electrical interconnection structure having a second plurality of electrical conductors extending from the second surface thereof, said interconnection structure adapted in use for contact locations of the second plurality of electrical conductors making pressure connections with a plurality of contact locations on a second space transformer. - View Dependent Claims (291, 292, 293, 294, 295, 296, 297, 316)
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298-315. -315. (canceled)
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317-597. -597. (canceled)
Specification