Intelligent probe card architecture

• US 20080100320A1
• Filed: 12/11/2007
• Published: 05/01/2008
• Est. Priority Date: 04/21/2004
• Status: Abandoned Application

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Henson, Roy, Chraft, Matthew, Miller, Charles
• Application Number:
  US12/001,281
• Publication Number:
  US 20080100320A1
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

Claims

1-35. -35. (canceled)

36. :

A test assembly for communicating test data between a test system controller and an unpackaged semiconductor device under test, the unpackaged semiconductor device designed for use in an operational environment, the test assembly comprising;

a probe card for providing connection to the test system controller to communicate test information with the test system controller and having a plurality of resilient probes configured to mechanically and electrically contact the unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device; and

circuitry comprising at least a portion of the operational environment.

37. :

The test assembly of claim 36, wherein the circuitry includes circuit portions of a personal computer motherboard.

38. :

The test assembly of claim 36, wherein an unpackaged semiconductor device is a microprocessor.

39. :

The test assembly of claim 36, wherein the probe card further comprises a probe support substrate and at least a portion of the circuitry resides on the probe support substrate.

40. :

The test assembly of claim 36, wherein the probe card further comprises a daughter card mechanically and electrically coupled to the probe card and wherein at least a portion of the circuitry resides on the daughter card.

37-1. :

The test assembly of claim 36, wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.

38-2. :

The test assembly of claim 36, wherein the probe card further comprises a wiring substrate and at least a portion of the circuitry resides on the wiring substrate.

41. :

A method of testing an unpackaged semiconductor device with a testing assembly, the unpackaged semiconductor device designed for use in an operational environment, the method comprising;

providing a probe card for making connection to a test system controller to communicate test information and having a plurality of resilient probes configured to mechanically and electrically contact the unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device;

providing circuitry including a portion of the operational environment;

bringing into contact the resilient probes and the unpackaged semiconductor device; and

testing the unpackaged semiconductor device with the circuitry to emulate a portion of the operational environment.

42. :

The method of claim 41, wherein the providing circuitry comprises providing support circuits from a desired motherboard configuration.

43. :

The method of claim 41, wherein the testing includes a power up sequence.

44. :

The method of claim 41, wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.

45. :

The method of claim 41, wherein the providing the circuitry comprises providing at least a portion of the circuitry on a wiring substrate.

46. :

The method of claim 41, wherein the providing the circuitry comprises providing at least a portion of the circuitry on a probe support substrate.

47. :

The method of claim 41, wherein the providing the circuitry comprises providing at least a portion of the circuitry on a daughter card mechanically and electrically coupled to the probe card.

48. :

A method of producing a tested semiconductor device, the semiconductor device designed for use in an operational environment, the method comprising;

providing a probe card for making connection to a test system controller to communicate test information and having a plurality of resilient probes configured to mechanically and electrically contact an unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device;

providing circuitry including a portion of the operational environment;

bringing into contact the resilient probes and the unpackaged semiconductor device; and

testing the unpackaged semiconductor device with the circuitry to emulate a portion of the operational environment.

49. :

The method of claim 48, wherein the providing circuitry comprises providing support circuits from a desired motherboard configuration.

50. :

The method of claim 48, wherein the testing includes a power up sequence.

51. :

The method of claim 48, wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.

52. :

The method of claim 48, wherein the providing circuitry comprises providing at least a portion of the circuitry on a wiring substrate.

53. :

The method of claim 48, wherein the providing circuitry comprises providing at least a portion of the circuitry on a probe support substrate.

54. :

The method of claim 48, wherein the providing circuitry comprises providing at least a portion of the circuitry on a daughter card mechanically and electrically coupled to the probe card.