FILTER OF ADJUSTABLE FREQUENCY RESPONSE AND METHOD THEREOF

• US 20080100372A1
• Filed: 10/26/2006
• Published: 05/01/2008
• Est. Priority Date: 10/26/2006
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lin, Chia-Liang
• Granted Patent: US 9,083,299 B2
• Time in Patent Office: Days
• US Class Current: 327/552
• CPC Class Codes: H03H 2/00 Networks using elements or techniques not provided for in groups H03H3/00 - H03H21/00
• CPC Class Codes: H03H 2250/00 Indexing scheme relating to dual- or multi-band filters

Abstract

A filter of an adjustable frequency response comprises a plurality of filters having a plurality of distinct frequency responses, respectively. These filters receive a common input signal and generate a plurality of intermediate signals, respectively. A multiplexing circuit is used to select one of these intermediate signals as a filtered signal. The multiplexing circuit is controlled by a control signal that is related to a state of the filtered signal.

Claims

1. A circuit comprising:

a plurality of filters of distinct frequency responses for receiving a common input signal and for generating a plurality of filtered signals, respectively; and

a multiplexing circuit, coupled to the plurality of the filters, controlled by a control signal for generating an output signal by selecting among said filtered signals.

2. The circuit of claim 1 further comprises a signal processor for generating the control signal by processing the output signal.

3. The circuit of claim 1, wherein said filters all have low output impedances that are substantially lower than the input impedances of their respective load circuits regardless of a state of the control signal.

4. The circuit of claim 1, wherein the output signal is terminated by a circuit having a high output impedance that is substantially higher than the output impedance of the multiplexing circuit regardless of a state of the control signal.

5. The circuit of claim 1, wherein the multiplexing circuit comprises a plurality of switches controlled by a plurality of signals derived from a state of the control signal.

6. The circuit of claim 1, wherein one of said filters is a passive circuit comprising a capacitor.

7. The circuit of claim 1, wherein one of said filters is an active circuit comprising an operational amplifier.

8. The circuit of claim 1, wherein at least one of said filters is powered down to save power when its corresponding filtered signal is not selected.

13. The receiver of claim 8, wherein the signal processor comprises at least part of the following functions:

analog-to-digital conversion, filtering, demodulation, detection, and timing synchronization.

9. A receiver comprising:

a front-end circuit for receiving an input signal and generating a processed signal;

a plurality of filters for receiving the processed signal and generating a plurality of intermediate signals, respectively;

a multiplexing circuit controlled by a control signal for generating a filtered signal by selecting among said intermediate signals; and

a signal processor for receiving the filtered signal to generate the control signal.

10. The receiver of claim 9, wherein the signal processor further comprising:

a back-end circuit for receiving the filtered signal and generating a digital data; and

a digital circuit for processing the digital data to generate an output data and the control signal.

11. The receiver of claim 9, wherein the multiplexing signal comprises a plurality of switches controlled by a plurality of signals derived from a state of the control signal.

12. The receiver of claim 9, wherein at least one of said filters is powered down to save power when its corresponding intermediate signal is not selected.

14. The receiver of claim 10, wherein the output data comprises a first segment and a second segment.

15. The receiver of claim 14, wherein a first intermediate signal among said intermediate signals is selected during when the digital circuit is receiving the first segment of the output data, and a second intermediate signal among said intermediate signals is selected during when the digital circuit is receiving the second segment of the output data.

16. A method for receiving an input signal, the method comprising:

processing the input signal using a front-end circuit to generate a processed signal;

filtering the processed signal using a plurality of filters to generate a plurality of intermediate signals, respectively;

selecting among said intermediate signals to generate a filtered signal based on a control signal; and

processing the filtered signal to generate the control signal.

17. The method of claim 16, wherein the step of processing the filtered signal comprising:

processing the filtered signal to generate a digital data; and

processing the digital data to generate an output data and the control signal.

18. A method of claim 16, wherein the step of selecting further comprises using a plurality of switches controlled by a plurality of signals derived from the state of the control signal.

19. The method of claim 16, wherein at least one of said filters is a passive filter comprising a capacitor.

20. The method of claim 16, wherein at least one of said filter is an active filter comprising an operational amplifier.

21. The method of claim 17, wherein the output data comprises a first segment and a second segment.

22. The method of claim 21, wherein the first segment is a preamble and the second segment is a payload.