Electrooptic device and electronic apparatus
First Claim
1. An electrooptic device having an image display period and an information gathering period, comprising:
- a panel unit including;
a first substrate;
a second substrate;
an electrooptic material interposed between the first and second substrates;
a plurality of first scan lines provided above the first substrate;
a plurality of second scan lines provided above the first substrate and disposed in parallel to the first scan lines;
a plurality of signal lines provided above the first substrate and intersecting the first scan lines and the second scan lines; and
a plurality of pixels provided above the first substrate and disposed at intersections of the first scan lines and the second scan lines and the signal lines, each pixel located in an i-th row and a j-th column, the i and the j being both natural numbers, including;
a first transistor;
a second transistor; and
a pixel electrode; and
a data processing unit, wherein;
the plurality of pixels are formed in a matrix on the first substrate;
a gate of the first transistor is coupled to the first scan line in the i-th row;
one of a source and a drain of the first transistor is coupled to the signal line on the j-th column;
a gate of the second transistor is coupled to the second scan line in the i-th row;
one of a source and a drain of the second transistor is coupled to the other of the source and drain of the first transistor; and
the other of the source and drain of the first transistor is coupled to the pixel electrode.
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Accused Products
Abstract
An electrooptic device having an image display period and an information gathering period includes a panel unit and a data processing unit. The panel unit includes a first substrate, a second substrate, an electrooptic material interposed between the first and second substrates, a plurality of first scan lines provided above the first substrate, a plurality of second scan lines provided above the first substrate and disposed in parallel to the first scan lines, a plurality of signal lines provided above the first substrate and intersecting the first scan lines and the second scan lines, and a plurality of pixels provided above the first substrate and disposed at intersections of the first scan lines and the second scan lines and signal lines. Each pixel located in an i-th row and a j-th column (i and j are both natural numbers) includes a first transistor, a second transistor, and a pixel electrode. The plurality of pixels are formed in a matrix on the first substrate. A gate of the first transistor is coupled to the first scan line in the i-th row. One of a source and a drain of the first transistor is coupled to the signal line on the j-th column. A gate of the second transistor is coupled to the second scan line in the i-th row. One of a source and a drain of the second transistor is coupled to the other of the source and drain of the first transistor. The other of the source and drain of the first transistor is coupled to the pixel electrode.
41 Citations
19 Claims
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1. An electrooptic device having an image display period and an information gathering period, comprising:
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a panel unit including;
a first substrate;
a second substrate;
an electrooptic material interposed between the first and second substrates;
a plurality of first scan lines provided above the first substrate;
a plurality of second scan lines provided above the first substrate and disposed in parallel to the first scan lines;
a plurality of signal lines provided above the first substrate and intersecting the first scan lines and the second scan lines; and
a plurality of pixels provided above the first substrate and disposed at intersections of the first scan lines and the second scan lines and the signal lines, each pixel located in an i-th row and a j-th column, the i and the j being both natural numbers, including;
a first transistor;
a second transistor; and
a pixel electrode; and
a data processing unit, wherein;
the plurality of pixels are formed in a matrix on the first substrate;
a gate of the first transistor is coupled to the first scan line in the i-th row;
one of a source and a drain of the first transistor is coupled to the signal line on the j-th column;
a gate of the second transistor is coupled to the second scan line in the i-th row;
one of a source and a drain of the second transistor is coupled to the other of the source and drain of the first transistor; and
the other of the source and drain of the first transistor is coupled to the pixel electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification
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- Resources
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Current Assignee138 East LCD Advancements Limited (Vector Capital Corporation)
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Original AssigneeSeiko Epson Corporation (Seiko Group)
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InventorsMiyasaka, Mitsutoshi, Kenmochi, Nobuhiko
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current345/107
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CPC Class CodesG09G 2300/0426 Layout of electrodes and co...G09G 2300/0439 Pixel structuresG09G 2300/0842 forming a memory circuit, e...G09G 2310/0251 Precharge or discharge of p...G09G 2320/029 by monitoring one or more p...G09G 3/3446 with more than two electrod...
