NAND FLASH MEMORY CELL PROGRAMMING
First Claim
1. A method of programming a memory cell in a flash memory having first and second addressable blocks of floating gate memory cells, the method comprising:
- pre-charging first word line conductors coupled to memory cells of the first addressable block to a first non-zero voltage level; and
charging second word line conductors coupled to memory cells of the second addressable block to either a second or third voltage level, wherein the second and third voltage levels are greater than the first voltage level.
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Abstract
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are described.
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Citations
25 Claims
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1. A method of programming a memory cell in a flash memory having first and second addressable blocks of floating gate memory cells, the method comprising:
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pre-charging first word line conductors coupled to memory cells of the first addressable block to a first non-zero voltage level; and
charging second word line conductors coupled to memory cells of the second addressable block to either a second or third voltage level, wherein the second and third voltage levels are greater than the first voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of programming a memory cell in a flash memory having first and second addressable blocks of floating gate memory cells, the method comprising:
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pre-charging word lines of the first addressable blocks to a first voltage level;
programming the memory cell in the second addressable block by biasing word lines of the second addressable block to a second voltage level; and
discharging the first and second word lines after programming the memory cell. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A flash memory method, comprising:
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pre-charging a plurality of word line conductors coupled to addressable arrays of floating gate transistors to a first non-zero voltage level; and
charging a plurality of global word line conductors to one of a second or a third voltage level, the second and third voltage levels are greater than the first voltage level, wherein the third voltage level is selectively coupled to one of the plurality of word lines for programming. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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Specification