NAND FLASH MEMORY CELL PROGRAMMING

• US 20080101123A1
• Filed: 01/04/2008
• Published: 05/01/2008
• Est. Priority Date: 08/04/2005
• Status: Active Grant

• Current Assignee: Seiichi Aritome
• Original Assignee: Seiichi Aritome
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,414,895 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are described.

Claims

1. A method of programming a memory cell in a flash memory having first and second addressable blocks of floating gate memory cells, the method comprising:

pre-charging first word line conductors coupled to memory cells of the first addressable block to a first non-zero voltage level; and

charging second word line conductors coupled to memory cells of the second addressable block to either a second or third voltage level, wherein the second and third voltage levels are greater than the first voltage level.

2. The method of claim 1, wherein the first level is about a supply voltage, VCC, of the memory device, the second voltage level is about 10 volts and the third voltage is about 20 volts.

3. The method of claim 1, wherein the first, second and third voltage levels are sourced by a common bias voltage circuit.

4. The method of claim 3, further comprising selectively coupling the first and second word line conductors to the common bias voltage circuit via a global word line conductor.

5. The method of claim 3, wherein the first word line conductors are pre-charged prior to charging the second word line conductors.

6. The method of claim 3, further comprises discharging the first and second word line conductors after programming the memory cell.

7. The method of claim 6, wherein pre-charging includes pre-charging the word lines of the first addressable blocks when data is programmed in the memory cell of the second addressable block.

8. The method of claim 1, wherein pre-charging includes pre-charging the word lines of the first addressable blocks during at least some of the programming operation.

9. A method of programming a memory cell in a flash memory having first and second addressable blocks of floating gate memory cells, the method comprising:

pre-charging word lines of the first addressable blocks to a first voltage level;

programming the memory cell in the second addressable block by biasing word lines of the second addressable block to a second voltage level; and

discharging the first and second word lines after programming the memory cell.

10. The method of claim 9, wherein the word lines of the first addressable blocks are pre-charged via a pre-charge circuit.

11. The method of claim 10, wherein the first and second word lines are discharged via the pre-charge circuit.

12. The method of claim 9, wherein the word lines of the first addressable blocks are pre-charged via global word lines.

13. The method of claim 12, wherein the first and second word lines are discharged via the global word lines.

14. The method of claim 9, wherein pre-charging includes pre-charging the word lines of the first addressable blocks when data is programmed in the memory cell of the second addressable block.

15. The method of claim 14, wherein pre-charging includes pre-charging the word lines of the first addressable blocks during at least some of the programming operation.

16. The method of claim 14, wherein pre-charging includes pre-charging the word lines of the first addressable blocks during all of the program operation.

17. The method of claim 14, wherein pre-charging includes pre-charging the word lines of the first addressable blocks prior to programming the memory cell in the second addressable block.

18. The method of claim 14, wherein pre-charging includes pre-charging the word lines of the first addressable blocks while programming the memory cell in the second addressable block.

19. A flash memory method, comprising:

pre-charging a plurality of word line conductors coupled to addressable arrays of floating gate transistors to a first non-zero voltage level; and

charging a plurality of global word line conductors to one of a second or a third voltage level, the second and third voltage levels are greater than the first voltage level, wherein the third voltage level is selectively coupled to one of the plurality of word lines for programming.

20. The method of claim 19, wherein pre-charging is limited to pre-charging word line conductors coupled to unselected addressable arrays of floating gate transistors.

21. The method of claim 19, wherein pre-charging occurs before charging.

22. The method of claim 19, wherein charging a plurality of global word line conductors includes removing a driver bias potential to decouple the global word line conductors from the word line conductors.

23. The method of claim 19, wherein pre-charging includes activating an isolation transistor to couple a pre-charge circuit to the word lines.

24. The method of claim 19, wherein pre-charging includes applying a voltage to reduce a transistor snap-back condition.

25. The method of claim 19, wherein pre-charging includes coupling a voltage to reduce a transistor punch-through condition.