HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS

• US 20080101149A1
• Filed: 10/22/2007
• Published: 05/01/2008
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Kenneth So, Luca Fasoli
• Inventors: So, Kenneth, Fasoli, Luca
• Granted Patent: US 7,633,829 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Claims

1. A method comprising:

decoding address information and selecting one or more array lines of a first type in a memory array using a first hierarchical decoder circuit comprising at least two hierarchical levels of multi-headed decoder circuits.

2. The method as recited in claim 1 wherein the decoding and selecting comprises:

decoding a plurality of address signal inputs using a first-level decoder circuit, and generating a plurality of first-level decoded outputs thereof;

coupling each respective first-level decoded output to a respective one of a plurality of second-level multi-headed decoder circuits, each providing a respective plurality of second-level decoded outputs; and

coupling each respective second-level decoded output to a respective one of a plurality of third-level multi-headed decoder circuits, each providing a respective plurality of third-level decoded outputs coupled to the memory array.

3. A method for making a product incorporating a memory array, said method comprising:

providing a memory array comprising array lines of first and second types coupled to memory cells;

providing a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type, said first hierarchical decoder circuit comprising at least two hierarchical levels of multi-headed decoder circuits.

4. The method as recited in claim 3 wherein said providing a first hierarchical decoder circuit comprises:

providing a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs;

providing a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs; and

providing a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.