Second order continuous time linear equalizer
First Claim
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1. A continuous time linear equalization circuit comprising:
- an input of a first stage to receive a differential input signal; and
an output of the first stage to output a differential output signal,wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, andwherein the differential output signal is not fed back to the first stage.
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Abstract
According to some embodiments, a continuous time linear equalization circuit includes an input of a first stage to receive a differential input signal, and an output of the first stage to output a differential output signal. A transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and the differential output signal is not fed back to the first stage.
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Citations
21 Claims
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1. A continuous time linear equalization circuit comprising:
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an input of a first stage to receive a differential input signal; and an output of the first stage to output a differential output signal, wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and wherein the differential output signal is not fed back to the first stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system comprising:
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a double data rate memory; and a microprocessor in communication with the memory, wherein the microprocessor includes a continuous time linear equalization circuit comprising; an input of a first stage to receive a differential input signal; and an output of the first stage to output a differential output signal, wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and wherein the differential output signal is not fed back to the first stage. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification