Second order continuous time linear equalizer

US 20080101450A1
Filed: 10/26/2006
Published: 05/01/2008
Est. Priority Date: 10/26/2006
Status: Abandoned Application

First Claim

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1. A continuous time linear equalization circuit comprising:

an input of a first stage to receive a differential input signal; and

an output of the first stage to output a differential output signal,wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, andwherein the differential output signal is not fed back to the first stage.

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Abstract

According to some embodiments, a continuous time linear equalization circuit includes an input of a first stage to receive a differential input signal, and an output of the first stage to output a differential output signal. A transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and the differential output signal is not fed back to the first stage.

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21 Claims

1. A continuous time linear equalization circuit comprising:
- an input of a first stage to receive a differential input signal; and
  
  an output of the first stage to output a differential output signal,wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, andwherein the differential output signal is not fed back to the first stage.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- - 2. A circuit according to claim 1, wherein the first stage comprises:
    - a first transistor, a gate of the first transistor to receive a first portion of the differential input signal;
      
      a second transistor, a gate of the second transistor to receive a second portion of the differential input signal;
      
      a capacitive element, a first node of the capacitive element coupled to a drain of the first transistor and a second node of the capacitive element coupled to a drain of the second transistor;
      
      a resistive element, a first node of the resistive element coupled to the drain of the first transistor and a second node of the resistive element coupled to the drain of the second transistor;
      
      a first current source, a first node of the first current source coupled to a supply voltage and a second node of the first current source coupled to the first node of the resistive element;
      
      a second current source, a first node of the second current source coupled to the supply voltage and a second node of the second current source coupled to the second node of the resistive element;
      
      a third transistor, a drain of the third transistor coupled to the supply power;
      
      a fourth transistor, a drain of the fourth transistor coupled to the supply power;
      
      a second resistive element, a first node of the second resistive element coupled to a gate of the third transistor and a second node of the second resistive element coupled to a source of the third transistor and to a first output node of the first stage, the first output node to output a first portion of the output differential signal; and
      
      a third resistive element, a first node of the third resistive element coupled to a gate of the fourth transistor and a second node of the third resistive element coupled to a source of the fourth transistor and to a second output node of the first stage, the second output node to output a second portion of the output differential signal.
  - 3. A circuit according to claim 2, further comprising:
    - a third current source, a first node of the third current source coupled to the supply power and a second node of the third current source coupled to the first output node; and
      
      a fourth current source, a first node of the fourth current source coupled to the supply power and a second node of the fourth current source coupled to the second output node,wherein at least one of the first, second and third resistive elements comprises an active transistor circuit.
  - 4. A circuit according to claim 2, wherein the transfer function comprises:
    - $\frac{g_{m 1}}{g_{m 2} (1 + g_{m 1} \frac{R_{s}}{2})} \frac{(1 + {sR}_{s} C_{s}) (1 + {sR}_{p} C_{g})}{(1 + s \frac{R_{s} C_{s}}{(1 + g_{m 1} \frac{R_{s}}{2})}) (1 + s \frac{C_{g} + C_{L}}{g_{m 2}} + s^{2} \frac{R_{p} C_{g} C_{L}}{g_{m 2}})},$ wherein R_sis a resistance of the resistive element, R_pis a resistance of the second and third resistive elements, gm₁is a transconductance of the first transistor and the second transistor, gm₂is a transconductance of the third transistor and the fourth transistor, C_gis a total capacitance at the gate of the third transistor and the fourth transistor, and C_Lis a total capacitance at the output.
  - 5. A circuit according to claim 2, wherein the second resistive element and the third resistive element each comprise a variable resistive element.
  - 6. A circuit according to claim 5, wherein the first and second current sources comprise elements of a current mirror.
  - 7. A circuit according to claim 5, further comprising a second stage comprising:
    - a fifth transistor, a gate of the fifth transistor to receive the first portion of the differential output signal;
      
      a sixth transistor, a gate of the sixth transistor to receive the second portion of the differential output signal;
      
      a seventh transistor, a source of the seventh transistor coupled to the supply power;
      
      a eighth transistor, a source of the eighth transistor coupled to the supply power;
      
      a fourth resistive element, a first node of the fourth resistive element coupled to a gate of the seventh transistor and a second node of the fourth resistive element coupled to a drain of the seventh transistor, to a source of the fifth transistor, and to a first output node of the second stage, the first output node to output a first portion of a second output differential signal; and
      
      a fifth resistive element, a first node of the fifth resistive element coupled to a gate of the eighth transistor and a second node of the fifth resistive element coupled to a drain of the eighth transistor, to a source of the sixth transistor, and to a second output node of the second stage, the second output node to output a second portion of the second output differential signal.
  - 8. A circuit according to claim 1, wherein the first stage comprises:
    - a first transistor, a gate of the first transistor to receive a first portion of the differential input signal;
      
      a second transistor, a gate of the second transistor to receive a second portion of the differential input signal;
      
      a capacitive element, a first node of the capacitive element coupled to a drain of the first transistor and a second node of the capacitive element coupled to a drain of the second transistor;
      
      a resistive element, a first node of the resistive element coupled to a drain of the first transistor and a second node of the resistive element coupled to a drain of the second transistor;
      
      a first current source, a first node of the first current source coupled to a supply voltage and a second node of the first current source coupled to the first node of the resistive element;
      
      a second current source, a first node of the second current source coupled to the supply voltage and a second node of the second current source coupled to the second node of the resistive element;
      
      a third transistor, a drain of the third transistor coupled to ground;
      
      a fourth transistor, a drain of the fourth transistor coupled to ground;
      
      a second resistive element, a first node of the second resistive element coupled to a gate of the third transistor and a second node of the second resistive element coupled to a source of the third transistor, to a source of the first transistor and to a first output node of the first stage, the first output node to output a first portion of the output differential signal; and
      
      a third resistive element, a first node of the third resistive element coupled to a gate of the fourth transistor and a second node of the third resistive element coupled to a source of the fourth transistor, to a source of the second transistor and to a second output node of the first stage, the second output node to output a second portion of the output differential signal.
  - 9. A circuit according to claim 8, further comprising:
    - a third current source, a first node of the third current source coupled to the first output node and a second node of the third current source coupled to ground; and
      
      a fourth current source, a first node of the fourth current source coupled to the second output node and a second node of the fourth current source coupled to ground,wherein at least one of the first, second and third resistive elements comprises an active transistor circuit.
  - 10. A circuit according to claim 8, wherein the transfer function comprises:
    - $\frac{g_{m 1}}{g_{m 2} (1 + g_{m 1} \frac{R_{s}}{2})} \frac{(1 + {sR}_{s} C_{s}) (1 + {sR}_{p} C_{g})}{(1 + s \frac{R_{s} C_{s}}{(1 + g_{m 1} \frac{R_{s}}{2})}) (1 + s \frac{C_{g} + C_{L}}{g_{m 2}} + s^{2} \frac{R_{p} C_{g} C_{L}}{g_{m 2}})},$ wherein R_sis a resistance of the resistive element, R_pis a resistance of the second and third resistive elements, gm₁is a transconductance of the first transistor and the second transistor, gm₂is a transconductance of the third transistor and the fourth transistor, C_gis a total capacitance at the gate of the third transistor and the fourth transistor, and C_Lis a total capacitance at the output.
  - 11. A circuit according to claim 8, wherein the second resistive element and the third resistive element each comprise a variable resistive element.

12. A system comprising:
- a double data rate memory; and
  
  a microprocessor in communication with the memory, wherein the microprocessor includes a continuous time linear equalization circuit comprising;
  
  an input of a first stage to receive a differential input signal; and
  
  an output of the first stage to output a differential output signal,wherein a transfer function between the input and the output exhibits two zeros and three poles in frequency domain, andwherein the differential output signal is not fed back to the first stage.
- View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
- - 13. A system according to claim 12, wherein the first stage comprises:
    - a first transistor, a gate of the first transistor to receive a first portion of the differential input signal;
      
      a second transistor, a gate of the second transistor to receive a second portion of the differential input signal;
      
      a capacitive element, a first node of the capacitive element coupled to a drain of the first transistor and a second node of the capacitive element coupled to a drain of the second transistor;
      
      a resistive element, a first node of the resistive element coupled to the drain of the first transistor and a second node of the resistive element coupled to the drain of the second transistor;
      
      a first current source, a first node of the first current source coupled to a supply voltage and a second node of the first current source coupled to the first node of the resistive element;
      
      a second current source, a first node of the second current source coupled to the supply voltage and a second node of the second current source coupled to the second node of the resistive element;
      
      a third transistor, a drain of the third transistor coupled to the supply power;
      
      a fourth transistor, a drain of the fourth transistor coupled to the supply power;
      
      a second resistive element, a first node of the second resistive element coupled to a gate of the third transistor and a second node of the second resistive element coupled to a source of the third transistor and to a first output node of the first stage, the first output node to output a first portion of the output differential signal; and
      
      a third resistive element, a first node of the third resistive element coupled to a gate of the fourth transistor and a second node of the third resistive element coupled to a source of the fourth transistor and to a second output node of the first stage, the second output node to output a second portion of the output differential signal.
  - 14. A system according to claim 13, further comprising:
    - a third current source, a first node of the third current source coupled to the supply power and a second node of the third current source coupled to the first output node; and
      
      a fourth current source, a first node of the fourth current source coupled to the supply power and a second node of the fourth current source coupled to the second output node,wherein at least one of the first, second and third resistive elements comprises an active transistor system.
  - 15. A system according to claim 13, wherein the transfer function comprises:
    - $\frac{g_{m 1}}{g_{m 2} (1 + g_{m 1} \frac{R_{s}}{2})} \frac{(1 + {sR}_{s} C_{s}) (1 + {sR}_{p} C_{g})}{(1 + s \frac{R_{s} C_{s}}{(1 + g_{m 1} \frac{R_{s}}{2})}) (1 + s \frac{C_{g} + C_{L}}{g_{m 2}} + s^{2} \frac{R_{p} C_{g} C_{L}}{g_{m 2}})},$ wherein R_sis a resistance of the resistive element, R_pis a resistance of the second and third resistive elements, gm₁is a transconductance of the first transistor and the second transistor, gm₂is a transconductance of the third transistor and the fourth transistor, C_gis a total capacitance at the gate of the third transistor and the fourth transistor, and C_Lis a total capacitance at the output.
  - 16. A system according to claim 13, wherein the second resistive element and the third resistive element each comprise a variable resistive element.
  - 17. A system according to claim 16, further comprising a second stage comprising:
    - a fifth transistor, a gate of the fifth transistor to receive the first portion of the differential output signal;
      
      a sixth transistor, a gate of the sixth transistor to receive the second portion of the differential output signal;
      
      a seventh transistor, a source of the seventh transistor coupled to the supply power;
      
      a eighth transistor, a source of the eighth transistor coupled to the supply power;
      
      a fourth resistive element, a first node of the fourth resistive element coupled to a gate of the seventh transistor and a second node of the fourth resistive element coupled to a drain of the seventh transistor, to a source of the fifth transistor, and to a first output node of the second stage, the first output node to output a first portion of a second output differential signal; and
      
      a fifth resistive element, a first node of the fifth resistive element coupled to a gate of the eighth transistor and a second node of the fifth resistive element coupled to a drain of the eighth transistor, to a source of the sixth transistor, and to a second output node of the second stage, the second output node to output a second portion of the second output differential signal.
  - 18. A system according to claim 12, wherein the first stage comprises:
    - a first transistor, a gate of the first transistor to receive a first portion of the differential input signal;
      
      a second transistor, a gate of the second transistor to receive a second portion of the differential input signal;
      
      a capacitive element, a first node of the capacitive element coupled to a drain of the first transistor and a second node of the capacitive element coupled to a drain of the second transistor;
      
      a resistive element, a first node of the resistive element coupled to a drain of the first transistor and a second node of the resistive element coupled to a drain of the second transistor;
      
      a first current source, a first node of the first current source coupled to a supply voltage and a second node of the first current source coupled to the first node of the resistive element;
      
      a second current source, a first node of the second current source coupled to the supply voltage and a second node of the second current source coupled to the second node of the resistive element;
      
      a third transistor, a drain of the third transistor coupled to ground;
      
      a fourth transistor, a drain of the fourth transistor coupled to ground;
      
      a second resistive element, a first node of the second resistive element coupled to a gate of the third transistor and a second node of the second resistive element coupled to a source of the third transistor, to a source of the first transistor and to a first output node of the first stage, the first output node to output a first portion of the output differential signal; and
      
      a third resistive element, a first node of the third resistive element coupled to a gate of the fourth transistor and a second node of the third resistive element coupled to a source of the fourth transistor, to a source of the second transistor and to a second output node of the first stage, the second output node to output a second portion of the output differential signal.
  - 19. A system according to claim 18, further comprising:
    - a third current source, a first node of the third current source coupled to the first output node and a second node of the third current source coupled to ground; and
      
      a fourth current source, a first node of the fourth current source coupled to the second output node and a second node of the fourth current source coupled to ground,wherein at least one of the first, second and third resistive elements comprises an active transistor system.
  - 20. A system according to claim 18, wherein the transfer function comprises:
    - $\frac{g_{m 1}}{g_{m 2} (1 + g_{m 1} \frac{R_{s}}{2})} \frac{(1 + {sR}_{s} C_{s}) (1 + {sR}_{p} C_{g})}{(1 + s \frac{R_{s} C_{s}}{(1 + g_{m 1} \frac{R_{s}}{2})}) (1 + s \frac{C_{g} + C_{L}}{g_{m 2}} + s^{2} \frac{R_{p} C_{g} C_{L}}{g_{m 2}})},$ wherein R_sis a resistance of the resistive element, R_pis a resistance of the second and third resistive elements, gm₁is a transconductance of the first transistor and the second transistor, gm₂is a transconductance of the third transistor and the fourth transistor, C_gis a total capacitance at the gate of the third transistor and the fourth transistor, and C_Lis a total capacitance at the output.
  - 21. A system according to claim 18, wherein the second resistive element and the third resistive element each comprise a variable resistive element.

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Current Assignee
Intel Corporation
Original Assignee
Intel Corporation
Inventors
Zou, Peng, Thenus, Fenardi, Wu, Zuoguo

Application Number

US11/586,920
Publication Number

US 20080101450A1
Time in Patent Office

Days
Field of Search
US Class Current

375/232
CPC Class Codes

H04L 25/0272   Arrangements for coupling t...

H04L 25/03878   Line equalisers; line build...

H04L 7/0054   Detection of the synchronis...

H04L 7/0337   Selecting between two or mo...

Second order continuous time linear equalizer

First Claim

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Abstract

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21 Claims

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Second order continuous time linear equalizer

First Claim

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Abstract

Citations

21 Claims

Specification

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