ELECTRICAL DIE CONTACT STRUCTURE AND FABRICATION METHOD

• US 20080102604A1
• Filed: 01/04/2008
• Published: 05/01/2008
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Owens, Alexander, Lee, Shaw, Patil, Sadanand, Prabhu, Ashok
• Granted Patent: US 7,795,126 B2
• Time in Patent Office: Days
• US Class Current: 438/461
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 23/4827 Materials
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Claims

1. A method for producing electrical die contact structures for integrated circuit devices, the method including the steps of:

providing a plurality of integrated circuits on a semiconductor wafer having a front side and a backside, each of the integrated circuits being delineated from other integrated circuits on the wafer by a plurality of saw streets and each integrated circuit including a multiplicity of electrical contact pads with contact pad extensions that extend into the saw streets;

attaching a front side protective layer to a front side surface of the wafer;

removing material from the backside of the wafer in the saw streets until a bottom surface of the contact pad extensions is exposed, thereby defining notches along edges of the integrated circuit devices;

forming electrical connections on the backside of the semiconductor substrate;

forming a backside metal layer such that a tail portion of the metal layer overlaps the bottom surface of the contact pad extensions and such that the contact pad extensions are electrically interconnected with electrical connections; and

separating the plurality of integrated circuit devices into individual devices.

2. The method of claim 1, wherein the providing step includes providing the semiconductor wafer wherein the electrical contact pads are separate from the contact pad extensions and are electrically interconnected using a bridge of conducting material.

3. The method of claim 1, wherein the providing step includes providing the semiconductor wafer wherein the integrated circuits comprise optical devices;

and

wherein attaching the front side protective layer comprises attaching an optically transmissive protective layer to a front side surface of the wafer using an optically transmissive adhesive material.

4. The method of claim 1, wherein the step of removing material from the backside of the wafer includes the step of thinning the wafer by removing material from the backside of the wafer.

5. The method of claim 1, wherein the step of forming electrical connections on the backside of the semiconductor substrate includes:

attaching a backside protective layer to a backside surface of the wafer with a backside adhesive,

forming electrical connections on a surface of the backside protective layer; and

wherein the step of forming a backside metal layer includes, removing the backside adhesive material and backside protective layer material in the saw streets and in the notches until a bottom surface of the contact pad extensions is exposed,

and forming the backside metal layer such that the tail portion of the metal layer overlaps the bottom surface of the contact pad extensions and such that the contact pad extensions are electrically interconnected with electrical connections on the backside protective layer.

6. The method of claim 5, wherein the step of forming electrical connections on the backside of the semiconductor substrate includes forming low modulus pads of material having a low coefficient of thermal expansion and forming solder balls on the low modulus pads.

7. The method of claim 1, wherein the step of forming the backside metal layer includes forming a layer of sealing material in the notch over the backside metal layer.

8. The method of claim 1, wherein the step of forming the backside metal layer includes:

forming the backside metal layer such that it includes an opening in the notch, thereby separating a backside metal layer of one integrated circuit from a backside metal layer of another adjacent integrated circuit, and includes forming a layer of sealing material in the notch over the backside metal layers such that is fills the opening.

9. A method for producing electrical die contact structures for integrated circuit devices, the method including the steps of:

providing a plurality of integrated circuits on a semiconductor wafer having a front side and a backside, each of the integrated circuits being delineated from other integrated circuits on the wafer by a plurality of saw streets and each integrated circuit including a multiplicity of electrical contact pads with contact pad extensions that extend into the saw streets;

attaching a front side protective layer to a front side surface of the wafer using a layer of epoxy;

thinning the semiconductor wafer by removing material from the backside of the wafer;

partial cutting into the backside of the wafer in the saw streets, until the front side of the wafer is nearly reached leaving a thin layer of remaining material, thereby defining notches along edges of the integrated circuit devices;

first removing of the thin layer of remaining material in the notches to expose a bottom surface of the contact pad extensions in the saw streets;

attaching a backside protective layer to a backside surface of the wafer using a layer of backside epoxy;

cutting through the backside protective layer and the backside epoxy in the saw streets and in the notches until the back surface of the contact pad extensions is nearly reached;

second removing of material in the notches to expose the bottom surface of the contact pad extensions in the saw streets;

forming backside electrical connections on a surface of the backside protective layer;

forming a backside metal layer on the backside of the wafer such that a portion of the metal layer overlaps the bottom surface of the contact pad extensions and electrically interconnects another portion of the metal layer with the electrical connections formed on the backside protective layer;

forming a layer of sealing material in the notch such that at least a portion of the backside metal contact layer is covered with the sealing material; and

separating the plurality of integrated circuit devices into individual devices.

10. A method as in claim 9, wherein the step of producing includes producing the multiplicity of electrical contact pads so that the electrical contact pads comprise inner contact pads that do not extend into the saw streets and wherein the contact pad extensions comprise outer contact pads that do extend into the saw streets, the inner and outer contact pads being electrically connected by a bridge of conducting material.