CONFIGURABLE INFINITE LOGIC SIGNAL PROCESSING NETWORK AND GENETIC COMPUTING METHOD OF DESIGNING THE SAME

• US 20080103995A1
• Filed: 10/31/2006
• Published: 05/01/2008
• Est. Priority Date: 10/31/2006
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Xiao, Weimin, Mohamed, Magdi A., Zhou, Chi
• Granted Patent: US 7,761,392 B2
• Time in Patent Office: Days
• US Class Current: 706/4
• CPC Class Codes: G06N 3/126 Evolutionary algorithms, e.g. genetic algorithms or genetic programming

Abstract

Signal processing networks (700, 800, 1008, 1010, 1012) that include a configurable infinite logic aggregator (100) that can be configured as an infinite logic AND gate and infinite logic OR gate or as other gates along a continuum of function between the two by adjusting control signal magnitudes and a configurable infinite logic signal inverter (500) are provided. A method of designing such networks that includes a genetic programming program (1802) e.g., a gene expression programming program (1600), for designing the network topology, in combination with a numerical optimization (1804), e.g., a hybrid genetic algorithm/differential evolution numerical optimization (1700) for setting control signal values of the network and optionally other numerical parameters is provided.

Claims

1. A signal processing network comprising:

a signal aggregator comprising a first signal input, a second signal input, a first signal output and a first control signal input, wherein said signal aggregator is configurable by applying a first variable magnitude control signal to said first control signal input, wherein setting said first variable magnitude control signal to a first magnitude configures said aggregator to operate as an infinite logic AND gate, wherein setting said first variable magnitude control signal to a second magnitude configures said aggregator to operate as an infinite logic OR gate, and wherein operation of said signal aggregator varies between said infinite logic AND gate and said infinite logic OR gate as said first variable magnitude control signal varies in magnitude between said first magnitude and said second magnitude;

an infinite logic signal inverter comprising a third signal input, a second signal output and a second control signal input, wherein an input-output relation of said infinite logic signal inverter is a function of a second variable magnitude control signal applied to said second control signal input; and

wherein, said signal aggregator and said infinite logic signal inverter are coupled.

2. The signal processing network according to claim 1 wherein said signal aggregator comprises:

a first adder comprising a first input coupled to said first signal input, a second input coupled to said second signal input and a first adder output;

a first multiplier comprising a first input coupled to said first signal input, a second input coupled to said second signal input and a first multiplier output;

a second multiplier comprising a first input coupled to said first multiplier output, a second input coupled said first control signal input and a second multiplier output;

a second adder comprising a first input coupled to said first adder output, a second input coupled to said second multiplier output, and a second adder output;

a third adder comprising a first input coupled to said first control signal input, a second input set to a constant, and a third adder output; and

a divider comprising a numerator input coupled to said second adder output, a denominator input coupled to said third adder output, and an divider output coupled to said first signal output of said aggregator.

3. The signal processing network according to claim 1 wherein said infinite logic signal inverter comprises:

a subtracter comprising a first input set to a constant;

a second input coupled to said third signal input of said infinite logic signal inverter, and a subtracter output;

a multiplier comprising a first input coupled to said third signal input of said infinite logic signal inverter, a second input coupled to said second control signal input of said infinite logic signal inverter, and a multiplier output;

an adder comprising a first input set to said constant, a second input coupled to said multiplier output, and an adder output;

a divider comprising a numerator input coupled to said subtracter output, a denominator input coupled to said adder output, and an output coupled to said second signal output of said infinite logic signal inverter.

4. The signal processing network according to claim 3 wherein said infinite logic signal inverter further comprises:

a comparator comprising a first input set to said constant, a second input coupled to said third signal input of said infinite logic signal inverter, and a comparator output;

a ROM storing a fixed value of zero, coupled to said second signal output of said infinite logic signal inverter, wherein said ROM has a first enable input coupled to said comparator output; and

wherein said subtracter, said multiplier, said adder, and said divider are included in a circuit block that includes a second enable input that is also coupled to said comparator output.

5. The signal processing network according to claim 1 wherein:

said signal aggregator operates according to a first piecewise equation;

6. The signal processing network according to claim 5 wherein:

said infinite logic signal inverter operates according to a second equation;

7. The signal processing network according to claim 6 wherein said signal aggregator and said infinite logic signal inverter comprise a microprocessor programmed according to said first equation and said second equation.

8. The signal processing network according to claim 1 wherein:

said infinite logic signal inverter operates according to an equation;

9. The signal processing network according to claim 1 comprising a plurality of signal aggregators.

10. The signal processing network according to claim 1 comprising a plurality of infinite logic signal inverters.

11. A pattern recognition system comprising:

a sensor for obtaining measurements of a subject to be recognized;

a feature vector extractor coupled to said sensor, wherein said feature vector extractor serves to produce feature vectors from said measurements;

one or more signal processing networks according to claim 1 coupled to said feature vector extractor for receiving said feature vectors produced by said feature vector extractor;

a decision logic coupled to said one or more signal processing networks according to claim 1 wherein said decision logic classifies said subject to be recognized based on output of said one or more signal processing networks according to claim 1.

12. A computer configured by software to decode an array representation of a signal processing network, wherein said computer is programmed by said software to:

execute a recursive routine that comprises;

receive a sequence of genes representing signal processing elements, and terminals including signal inputs;

check if a first gene of said sequence of genes encodes a signal processing element, if said first gene does not encode a signal processing element terminating, and if said first gene does encode a signal processing element;

set a total number of children for said first gene to a number of inputs of said signal processing element;

initialize a first gene pointer to point to a second gene of said sequence following said first gene;

initialize a children counter;

associate said second gene with said first gene as a child of said first gene;

determine a length of a portion of said sequence of genes that encodes a sub-tree rooted by said child, wherein said sub-tree is part of a tree representation of the signal processing network;

recursively apply this recursive routine to said sequence of genes that encodes said sub-tree;

if said first gene has more children;

increment said children counter to indicate a next child;

set said first gene pointer to point to said next child in said sequence of genes which follows said portion of said sequence of genes; and

associate said next child with said first gene as a child of said first gene; and

return to said step of determining for said next child; and

If said first gene does not have more children, terminate.

13. The computer configured by software according to claim 12, wherein, in determining said length of said portion of said sequence of genes that encodes said sub-tree rooted by said child comprises, said computer is programmed to:

initialize a second gene pointer to point to said child;

initialize a required gene variable;

until the required gene variable is equal to zero;

increment the required gene variable by a number of signal inputs of a signal processing element coded by a current gene minus one;

increment the second pointer to point to a next gene; and

when said required gene variable is equal to zero, report said length that is based on said second gene pointer value.

14. The computer configured by software according to claim 13 wherein:

said second gene pointer is initialized to zero, wherein said child is considered a zeroth gene of said portion; and

reporting said length comprises reporting said second gene pointer.

15. The computer according to claim 12 further configured by software to evaluate output of the signal processing network in response to particular inputs, by:

starting at said first gene of said sequence of genes that represents a root in said tree representation of said signal processing network, and recursively applying a procedure of;

evaluating each child gene of each gene; and

using values output by each child gene to evaluate said gene,

whereby, terminal values are propagated through said tree representation of said signal processing network to an output of said root in said tree representation.

16. A computer configured by software to:

generate an initial population including a plurality of representations of signal processing networks that includes a logical aggregator signal processing element and a logical inverter signal processing element;

for each of a succession of generations of said population derived from said initial population;

check if a fitness goal has been achieved by one or more signal processing networks represented in said population;

if said fitness goal has been achieved;

output information relative to one or more signal processing networks that achieved said fitness goal;

if said fitness goal has not been achieved;

selectively replicate said plurality of representations for a next generation based on, at least, a fitness measure; and

perform evolutionary operations on said next generation.

17. The computer according to claim 16 wherein, in checking if said fitness goal has been achieved by one or more signal processing networks represented in said population, said computer is programmed by software to evaluate an overall fitness measure that includes a performance related fitness measure and a parsimony related fitness measure.

18. The computer according to claim 16, wherein said computer is configured by software to:

represent each signal processing network by a chromosome array, that includes gene elements that represent signal processing elements and one or more signal sources; and

in performing evolutionary operations on said next generation, said computer performs one or more evolutionary operations selected from a group consisting of one-point crossover two-point crossover, and mutation.

19. The computer configured by software according to claim 16 wherein:

said logical aggregator signal processing element, comprises an infinite logic aggregator that is configurable by adjusting a first magnitude of a first control signal;

said logical inverter signal processing element, comprises a infinite logic signal inverter that is configurable by adjusting a second magnitude of a second control signal; and

wherein for each of said succession of generations of said population derived from said initial population;

prior to checking if said fitness goal has been achieved;

said computer is programmed to numerically optimize said first magnitude and said second magnitude.

20. The computer according to claim 19 wherein, in numerically optimizing said first magnitude and said second magnitude, said computer is configured by software to:

generate an initial population including a plurality of sets of numerical parameters to be used with each signal processing network, wherein said sets of numerical parameters include said first magnitude and said second magnitude;

for each of a succession of generations of said population of said plurality of sets of numerical parameters;

evaluate a measure of performance related fitness for each signal processing network when configured with each of said plurality of sets of numerical parameters;

check, at least, if a performance related fitness criteria has been satisfied;

if, at least, said performance related fitness criteria has not been satisfied;

selected a next generation of sets of numerical parameters from a current generation of sets of numerical parameters based, at least in part, on said performance related fitness;

perform evolutionary operations on said next generation of sets of numerical parameters;

if, at least, said performance related fitness criteria has been satisfied;

return a set of numerical parameters that yield a best performance.

21. The computer according to claim 20 wherein, in performing said evolutionary operations on said next generation of sets of numerical parameters, said computer is configured by software to:

perform differential evolution mutation.

22. The computer configured by software according to claim 19 wherein:

said infinite logic aggregator varies continuously from an infinite logic AND operator to an infinite logic OR operator as a function of said first magnitude.

23. The computer according to claim 16 further configured by software to:

check that each of said plurality of representations of signal processing networks encodes a valid signal processing network.

24. The computer according to claim 23, wherein said computer is configured by software to:

represent each signal processing network by a chromosome array, that includes gene elements that represent signal processing elements and one or more signal sources; and

wherein, in checking that each of said plurality of representations of signal processing networks encodes a valid signal processing network, said computer is programmed to;

read a maximum chromosome length;

set an index that points to successive gene elements to an initial value;

initialize a required gene variable;

until said required gene variable is equal to zero OR said index is equal to said maximum chromosome length;

increase said required gene variable by one less than a number of inputs required for a signal processing element coded by a gene element identified by said index that points to successive gene elements; and

increment said index that points to successive gene elements;

after, said required gene variable is equal to zero OR said index is equal to said maximum chromosome length check if said required gene variable is greater than zero and if so returning an invalid chromosome indication.