STATES ENCODING IN MULTI-BIT FLASH CELLS FOR OPTIMIZING ERROR RATE

• US 20080104312A1
• Filed: 10/25/2007
• Published: 05/01/2008
• Est. Priority Date: 03/14/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Granted Patent: US 8,055,972 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2^M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Claims

1. A method of storing M≧

3 data bits in a memory cell, comprising the steps of;

(a) using a map from a logical ordering of patterns of M bits to a physical ordering of patterns of M bits, each entry of said logical ordering and a corresponding entry thereof of said physical ordering corresponding to a respective physical state of the memory cell, wherein said logical ordering is evenly distributed and said physical ordering is not evenly distributed;

mapping the M data bits into one of said entries of said physical ordering; and

(b) programming the memory cell to be in said physical state that corresponds to said one entry of said physical ordering.

2. The method of claim 1, further comprising the step of:

(c) reading said M bits from the cell.

3. The method of claim 2, wherein said reading includes translating an entry, of said physical ordering, that corresponds to a state of the cell, into a corresponding entry in said logical ordering.

4. The method of claim 1, wherein said logical ordering substantially equalizes probability-weighted numbers of transitions of all said M bits.

5. The method of claim 1, wherein both said physical ordering and said logical ordering have a total number of transitions equal to 2^M−

1.

6. The method of claim 5, wherein M=3 and wherein both said physical ordering and said logical ordering have 7 transitions.

7. The method of claim 6, wherein said physical ordering is one of {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}.

8. The method of claim 5, wherein M=4 and wherein both said physical ordering and said logical ordering have 15 transitions.

9. The method of claim 1, wherein M=4, and wherein a number of transitions of any bit of said logical ordering is selected from the group consisting of 3 and 4.

10. The method of claim 1, wherein said physical ordering is nonserial.

11. The method of claim 1, wherein said physical ordering is a valid ordering.

12. A memory device comprising:

(a) a memory that includes at least one cell; and

(b) a controller operative, upon receipt of M data bits to be stored in said memory, to store said M data bits in one of said at least one cell by steps including;

(i) using a map from a logical ordering of patterns of M bits to a physical ordering of patterns of M bits, each entry of said logical ordering and a corresponding entry thereof of said physical ordering corresponding to a respective physical state of said one cell, wherein said logical ordering is evenly distributed and said physical ordering is not evenly distributed;

mapping said M data bits into one of said entries of said physical ordering; and

(ii) programming said one cell to be in said physical state that corresponds to said one entry of said physical ordering.

13. The memory device of claim 12, wherein said controller effects said mapping by executing software.

14. The memory device of claim 12, wherein said controller includes dedicated hardware for effecting said mapping.

15. The memory device of claim 12, wherein said memory is a flash memory.

16. The memory device of claim 12, wherein said physical ordering is nonserial.

17. The memory device of claim 12, wherein said physical ordering is a valid ordering.

18. A system for storing data, comprising:

(a) a memory device that includes a memory, said memory including at least one cell;

(b) a host of said memory device, for providing M data bits to store; and

(c) a mechanism for storing said M data bits in one of said at least one cell by steps including;

(i) using a map from a logical ordering of patterns of M bits to a physical ordering of patterns of M bits, each entry of said logical ordering and a corresponding entry thereof of said physical ordering corresponding to a respective physical state of said one cell, wherein said logical ordering is evenly distributed and said physical ordering is not evenly distributed;

mapping said M data bits into one of said entries of said physical ordering; and

(ii) programming said one cell to be in said physical state that corresponds to said one entry of said physical ordering.

19. The system of claim 18, wherein said mechanism effects said mapping by executing software.

20. The system of claim 19, wherein said mechanism is included in said host.

21. The system of claim 19, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.

22. The system of claim 18, wherein said mechanism includes dedicated hardware for effecting said translating.

23. The system of claim 22, wherein said mechanism is included in said memory.

24. The system of claim 22, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.

25. The system of claim 18, wherein said memory is a flash memory.

26. The system of claim 18, wherein said physical ordering is nonserial.

27. The system of claim 18, wherein said physical ordering is a valid ordering.

28. A memory device comprising a memory that includes:

(a) at least one cell; and

(b) dedicated hardware operative, upon receipt of M data bits to be stored in said memory, to store said M data bits in one of said at least one cell by steps including;

(i) using a map from a logical ordering of patterns of M bits to a physical ordering of patterns of M bits, each entry of said logical ordering and a corresponding entry thereof of said physical ordering corresponding to a respective physical state of said one cell, wherein said logical ordering is evenly distributed and said physical ordering is not evenly distributed;

mapping said M data bits into one of said entries of said physical ordering; and

(ii) programming said one cell to be in said physical state that corresponds to said one entry of said physical ordering.

29. The memory device of claim 28, wherein said memory is a flash memory.

30. The memory device of claim 28, wherein said physical ordering is nonserial.

31. The memory device of claim 28, wherein said physical ordering is a valid ordering.

32. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering that is different from said physical bit ordering.

33. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌

N/K┐

of said bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering, wherein M is at least 3.

34. A system for storing data, comprising:

(a) a memory device that includes a memory, said memory including K cells;

(b) a host of said memory device, for providing N bits of data to store; and

(c) a mechanism for translating, for each said cell, up to M=┌

N/K┐

of said bits, as listed in an evenly distributed logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from said logical bit ordering, wherein M is at least 3, said each cell then being programmed according to said entry in said physical bit ordering.

35. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.

36. The method of claim 35, wherein a total number of transitions in said bit ordering is a minimum said number of transitions.

37. The method of claim 35, wherein said bit ordering has a total number of transitions equal to 2^M−

1.

38. The method of claim 37, wherein M=3 and wherein said bit ordering has seven said transitions.

39. The method of claim 38, wherein said bit ordering is selected from the group consisting of {7,6,4,5,10,2,3} and {7,6,4,5,1,3,2,0}.

40. The method of claim 37, wherein M=4 and wherein said bit ordering has fifteen said transitions.

41. The method of claim 35, wherein said bit ordering is evenly distributed.

42. The method of claim 41, wherein M=4 and wherein each bit of said bit ordering has at least three transitions and at most four transitions.

43. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each cell with up to M=┌

N/K┐

of said bits according to a valid, nonserial, error-rate-optimal bit ordering wherein M is at least 3.