Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtainable with Such a Method

• US 20080105922A1
• Filed: 12/19/2007
• Published: 05/08/2008
• Est. Priority Date: 03/12/2004
• Status: Abandoned Application

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), Koninklijke Philips N.V.
• Inventors: Pawlak, Bartlomiej
• Application Number:
  US11/960,382
• Publication Number:
  US 20080105922A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region and with a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region and with a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, and wherein both gate regions are formed within a trench formed in the semiconductor body.

Claims

1-9. -9. (canceled)

10. A semiconductor device comprising a dual gate field effect transistor, wherein the dual gate field effect transistor comprises:

a semiconductor body with a surface and comprising silicon;

a source region and a drain region of a first conductivity type;

a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region, wherein the first gate region is formed within a first trench;

a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, wherein the second gate region is formed within a second trench, wherein both gate regions are formed within a trench formed in the semiconductor body, and wherein the channel region is formed by the part of the semiconductor body between the first and second trench and the source and drain regions are formed at the surface of the semiconductor body.

11. The semiconductor device as claimed in claim 10, further comprising a second neighboring dual gate transistor with one gate region in common to both transistors.