Semiconductor device

• US 20080105934A1
• Filed: 12/21/2007
• Published: 05/08/2008
• Est. Priority Date: 06/15/2005
• Status: Abandoned Application

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Hsu, Heng Kai
• Application Number:
  US12/003,346
• Publication Number:
  US 20080105934A1
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The present gate structure comprises a gate oxide layer positioned on a substrate, a conductive stack positioned on the gate oxide layer, a passivation layer positioned on the sidewall of the conductive stack, and a cap layer positioned on the conductive stack. The conductive stack includes a polysilicon layer, a tungsten nitride layer, and a tungsten layer. The passivation layer can be made of silicon oxide, silicon nitride, or silicon oxynitride. The present method for preparing the gate structure comprises steps of forming a gate oxide layer, a conductive stack, and a cap layer on a semiconductor substrate in sequence, removing a portion of the gate oxide layer, the conductive stack, and the cap layer to form at least one opening, implanting silicon ions into the sidewall of the conductive stack, and performing a thermal treating process to transform the sidewall with silicon ions into a passivation layer.

Claims

1. A semiconductor device, comprising:

a gate stack positioned on a semiconductor substrate, the gate stack including a gate oxide layer positioned on the semiconductor substrate and a metal-containing layer positioned on the gate oxide layer;

a cap layer positioned on the metal-containing layer;

a spacer positioned on the sidewall of the gate stack; and

a passivation layer positioned between the gate stack and the spacer, and the passivation layer being configured to prevent the gate stack from corrosion.

2. The semiconductor device of claim 1, further comprising a metal silicide layer surrounding around the metal-containing layer and between the metal-containing layer and the passivation layer.

3. The semiconductor device of claim 2, wherein the metal silicide layer is formed by an ion implanting process.

4. The semiconductor device of claim 1, wherein the thickness of the passivation layer is between 2 and 15 nanometers.

5. The semiconductor device of claim 1, wherein the passivation layer is formed by a thermal treating process to transform a predetermined portion of the sidewall implanted with silicon ions into the passivation layer.

6. The semiconductor device of claim 1, wherein the passivation layer is formed by a selective oxidation process performed in an atmosphere including hydrogen and steam, and the passivation is made of silicon oxide.

7. The semiconductor device of claim 1, wherein the passivation layer is formed by an oxidation process performed in an oxygen atmosphere, and the passivation layer is made of silicon oxide.

8. The semiconductor device of claim 1, wherein the passivation layer is formed by a nitridation process performed in an atmosphere including ammonia gas, and the passivation layer is made of silicon nitride.

9. The semiconductor device of claim 1, wherein the passivation layer is formed by an oxynitridation process performed in a nitrous oxide atmosphere, and the passivation layer is made of silicon oxynitride.

10. The semiconductor device of claim 3, wherein the metal silicide layer is formed by a tilt implanting process.