HIGH POWER INSULATED GATE BIPOLAR TRANSISTORS

• US 20080105949A1
• Filed: 06/18/2007
• Published: 05/08/2008
• Est. Priority Date: 08/17/2006
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Agarwal, Anant K., Zhang, Qingchun, Ryu, Sei-Hyung, Jonas, Charlotte
• Granted Patent: US 8,710,510 B2
• Time in Patent Office: Days
• US Class Current: 257/584
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

Claims

1. An insulated gate bipolar transistor, comprising:

a substrate having a first conductivity type;

a drift layer having a second conductivity type opposite the first conductivity type;

a well region in the drift layer and having the first conductivity type;

a epitaxial channel adjustment layer on the drift layer and having the second conductivity type;

an emitter region extending from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region, the emitter region having the second conductivity type and at least partially defining a channel region in the well region adjacent to the emitter region;

a gate oxide layer on the channel region; and

a gate on the gate oxide layer.

2. The transistor of claim 1, wherein the drift layer comprises a JFET region adjacent to the well region, and wherein the emitter region is spaced apart from the JFET region and defines the channel region between the emitter region and the JFET region.

3. The transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

4. The transistor of claim 1, further comprising:

a connector region of the first conductivity type extending from a surface of the channel adjustment layer into the well region;

a first ohmic contact on the connector region;

a second ohmic contact on the emitter region and comprising a material different from the first ohmic contact; and

a metal overlayer electrically connecting the first ohmic contact and the second ohmic contact.

5. The transistor of claim 4, wherein the first ohmic contact comprises a nickel-based conductive material and wherein the second ohmic contact comprises an aluminum-based conductive material.

6. The transistor of claim 1, wherein the channel adjustment layer has a thickness of about 0.25 μ

m or more.

7. The transistor of claim 1, wherein a distance from a bottom of the emitter region to a bottom of the well region is about 0.45 μ

m or more.

8. The transistor of claim 1, wherein the channel adjustment layer has a thickness of about 0.1 μ

m to about 0.5 μ

m and a net doping concentration of about 1×

10¹⁶ cm<sup>−

3</sup> to about 5×

10¹⁸ cm<sup>−

3</sup>.

9. The transistor of claim 1, wherein the substrate comprises a silicon carbide substrate and wherein the drift layer comprises a silicon carbide epitaxial layer on the substrate.

10. A transistor, comprising:

an n-type substrate;

a p-type drift layer;

an n-type well in the drift layer;

a p-type channel adjustment layer on the drift layer;

a p-type emitter region extending through the channel adjustment layer and into the n-type well, the p-type emitter region at least partially defining a channel region in the n-type well adjacent the p-type emitter region;

an n-type connector region extending through the channel adjustment layer and into the n-type well;

a first ohmic contact including aluminum on the p-type emitter region;

a second ohmic contact including nickel on the n-type connector region;

a gate oxide layer on the channel region;

a gate on the gate oxide layer;

an interlayer dielectric layer on the gate, the interlayer dielectric layer including a first opening exposing the first ohmic contact and a second opening exposing the second ohmic contact; and

a metal overlayer on the interlayer dielectric layer and electrically connecting the first ohmic contact and the second ohmic contact.

11. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:

forming a p-type drift layer on an n-type substrate;

forming an n-type well in the p-type drift layer;

epitaxially growing a p-type channel adjustment layer on the p-type drift layer and on the n-type well;

implanting p-type dopant ions to form a p-type emitter region extending through the channel adjustment layer and into the n-type well at a surface of the drift layer, the p-type emitter region at least partially defining a channel region in the n-type well adjacent the p-type emitter region;

implanting n-type dopant ions to form an n-type connector region extending through the channel layer and into the n-type well at a surface of the drift layer;

annealing the implanted ions;

forming a gate oxide layer on the channel region; and

forming a gate on the gate oxide layer.

12. The method of claim 11, further comprising:

forming a graphite coating on the channel adjustment layer, wherein annealing the implanted ions comprises annealing the channel adjustment layer and the graphite coating; and

removing the graphite coating after annealing the implanted ions.

13. The method of claim 12, further comprising crystallizing the graphite coating before annealing the implanted ions.

14. The method of claim 12, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1700°

C.

15. The method of claim 12, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1800°

C.

16. The method of claim 11, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O₂, the method further comprising annealing the gate oxide layer in wet O₂.

17. The method of claim 16, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O₂ at a temperature less than or equal to about 1200°

C.

18. The method of claim 16, further comprising annealing the gate oxide layer in an inert atmosphere at a temperature less than or equal to about 1200°

C. after forming the gate oxide layer and before annealing the gate oxide layer in wet O₂.

19. The method of claim 16, wherein annealing the gate oxide layer in wet O₂ comprises annealing the gate oxide layer in wet O₂ at a temperature less than or equal to about 950°

C.

20. The method of claim 19, wherein annealing the gate oxide layer in wet O₂ comprises annealing the gate oxide layer in wet O₂ for at least one hour.

21. The method of claim 16, wherein annealing the oxide layer in wet O₂ comprises generating pyrogenic steam in a pyrogenic chamber, supplying the pyrogenic steam to an anneal chamber, and annealing the oxide layer in the anneal chamber.

22. The method of claim 21, wherein generating pyrogenic steam comprises heating the pyrogenic chamber, supplying hydrogen and oxygen gas to the pyrogenic chamber, and combusting the hydrogen gas and the oxygen gas to form the pyrogenic steam, wherein the hydrogen gas and the oxygen gas are supplied to the pyrogenic chamber at a molecular ratio of hydrogen to oxygen of about 1.8 or more.

23. The method of claim 11, further comprising implanting p-type dopant ions into the drift layer to form a JFET region adjacent to the n-type well, and wherein the p-type emitter region is spaced apart from the JFET region and defines a channel region between the p-type emitter region and the JFET region.

24. The method of claim 11, wherein the channel adjustment layer is formed to have a thickness of about 0.1 μ

m to about 0.5 μ

m, and wherein the channel adjustment layer has a net acceptor concentration of about 1×

10¹⁶ cm<sup>−

3</sup> to about 5×

10¹⁸ cm<sup>−

3</sup>.

25. The method of claim 11, wherein the substrate comprises silicon carbide, and wherein the drift layer comprises an epitaxial silicon carbide layer.