SEMICONDUCTOR CONSTRUCTIONS AND SEMICONDUCTOR DEVICE FABRICATION METHODS

• US 20080105969A1
• Filed: 12/27/2007
• Published: 05/08/2008
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis, Joshi, Rajiv, Mandelman, Jack
• Granted Patent: US 7,560,310 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10158 at the passive surface
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/96 Porous semiconductor
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Claims

1. A method of fabricating a semiconductor device, comprising:

etching a substrate formed on a backside of a semiconductor wafer to form a recess in said substrate; and

forming a sputter film in said recess, said sputter film including;

a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of said substrate; and

a second material having a thermal conductivity which is greater than a thermal conductivity of said substrate.

2. The method of claim 1, wherein a first portion of said sputter film includes a concentration of said first material which is greater than a concentration of said second material.

3. The method of claim 2, wherein a second portion of said sputter film includes a concentration of said second material which is greater than a concentration of said first material.

4. The method of claim 3, wherein a third portion of said sputter film is formed between said first and second portions and includes a graded portion which gradually transitions between said first and second portions.

5. The method of claim 1, further comprising:

mounting a heat sink on said sputter film.

6. The method of claim 5, wherein said heat sink has a CTE which is at least substantially equal to a CTE of said second material.

7. The method of claim 1, wherein said first material comprises a semiconductor and said second material comprises a metal.

8. The method of claim 1, wherein said first material comprises silicon and said second material comprises aluminum.

9. The method of claim 1, wherein said wafer includes a silicon-on-insulator wafer including a buried insulating layer.

10. The method of claim 1, further comprising:

forming a barrier layer on a backside of said buried insulating layer,

wherein a thickness of a frontside of said wafer between an uppermost surface of said wafer and said barrier layer is in a range from about 10 to about 20% of a total thickness of said wafer.

11. A semiconductor device comprising:

a substrate formed on a backside of a semiconductor wafer, the substrate including a recess; and

a conversion region formed in said substrate, said conversion region including at least one of;

an interdiffusion layer including a material having a thermal conductivity greater than a thermal conductivity of said substrate which is formed in pores of said substrate in said area of said recess, and a layer of said material formed on said interdiffusion layer; and

a sputter film formed in said recess, said sputter film including;

a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of said substrate; and

a second material having a thermal conductivity which is greater than a thermal conductivity of said substrate.

12. The semiconductor device of claim 11, wherein a first portion of said sputter film includes a concentration of said first material which is greater than a concentration of said second material.

13. The semiconductor device of claim 12, wherein a second portion of said sputter film includes a concentration of said second material which is greater than a concentration of said first material.

14. The semiconductor device of claim 13, wherein a third portion of said sputter film is formed between said first and second portions and includes a graded portion which gradually transitions between said first and second portions.

15. The semiconductor device of claim 11, further comprising:

a heat sink which is mounted on said sputter film.

16. The semiconductor device of claim 15, wherein said heat sink has a CTE which is at least substantially equal to a CTE of said second material.

17. The semiconductor device of claim 11, wherein said first material comprises a semiconductor and said second material comprises a metal.

18. The semiconductor device of claim 11, wherein said first material comprises silicon and said second material comprises aluminum.

19. The semiconductor device of claim 11, wherein said wafer includes a silicon-on-insulator wafer including a buried insulating layer.

20. The semiconductor device of claim 11, further comprising:

a barrier layer formed on a backside of said buried insulating layer,

wherein a thickness of a frontside of said wafer between an uppermost surface of said wafer and said barrier layer is in a range from about 10 to about 20% of a total thickness of said wafer.