SIGNAL PROCESSING SYSTEM AND METHOD

• US 20080106273A1
• Filed: 10/31/2007
• Published: 05/08/2008
• Est. Priority Date: 12/21/2003
• Status: Active Grant

• Current Assignee: TK Holdings Incorporated (Ningbo Junsheng Investment Group Co., Ltd.)
• Original Assignee: TK Holdings Incorporated (Ningbo Junsheng Investment Group Co., Ltd.)
• Inventors: BAAL, James, BAUER, Scott
• Granted Patent: US 7,564,249 B2
• Time in Patent Office: Days
• US Class Current: 324/656
• CPC Class Codes: G01D 5/202 by movable a non-ferromagnetic conductive element G01D5/2033 takes precedence
• CPC Class Codes: G01D 5/2053 by a movable non-ferromagnetic conductive element
• CPC Class Codes: G01R 33/0283 in which a current or voltage is generated due to relative movement of conductor and magnetic field
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: G01R 33/09 Magnetoresistive devices

Abstract

First and second complementary voltage signals are operatively coupled across a series circuit comprising first and second sense resistors and a circuit element therebetween. A voltage across the circuit element is regulated in reference to a predetermined level, and an output signal responsive to the self-impedance of the circuit element is generated responsive at least one of a voltage across the first sense resistor and a voltage across the second sense resistor.

Claims

1. A method of processing a signal responsive to a self-impedance of a circuit element, comprising:

a. generating first and second complementary voltage signals, wherein said first and second complementary voltage signals comprise respective first and second oscillatory voltage signals having a nominal peak amplitude, and said second oscillatory voltage signal comprises a waveform of said first oscillatory voltage signal shifted in phase by substantially 180 degrees;

b. operatively coupling said first complementary voltage signal to a first node of a series circuit;

c. operatively coupling said second complementary voltage signal to a fourth node of said series circuit, wherein said series circuit comprises;

i) a first sense resistor between said first node and a second node; and

ii) a second sense resistor between a third node and said fourth nodes, wherein said series circuit is completed by connecting said second and third nodes to the circuit element;

d. regulating a voltage across said second and third nodes in reference to a predetermined level; and

e. generating an output signal responsive to at least one of a voltage across said first sense resistor and a voltage across said second sense resistor, wherein said output signal is responsive to the self-impedance of said circuit element when said circuit element is connected to said second and third nodes of said series circuit.

2. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein the operations of regulating said voltage across said second and third nodes, and operatively coupling said first and second complementary voltage signals to said first and fourth nodes of said series circuit comprise:

a. applying said first complementary voltage signal to an input of a first amplifier;

b. operatively coupling said second node of said series circuit to said input of said first amplifier;

c. applying said second complementary voltage signal to an input of a second amplifier;

d. operatively coupling said third node of said series circuit to said input of said second amplifier; and

e. operatively coupling an output of said second amplifier to said fourth node of said series circuit.

3. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 2, wherein said first amplifier comprises a first operational amplifier and said second amplifier comprises a second operational amplifier, further comprising:

f. operatively coupling said first complementary voltage signal through a first input resistor to an inverting input of said first operational amplifier;

g. operatively coupling said second node of said series circuit through a first feedback resistor to said inverting input of said first operational amplifier;

h. operatively coupling said second complementary voltage signal through a second input resistor to an inverting input of said second operational amplifier; and

i. operatively coupling said third node of said series circuit through a second feedback resistor to said inverting input of said second operational amplifier.

4. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 2, wherein a gain of said first amplifier is substantially unity, and a gain of said second amplifier is substantially unity.

5. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 3, wherein said first complementary voltage signal comprises a first bias voltage signal, said second complementary voltage signal comprises a second bias voltage signal, said first and second bias voltage signals are substantially equal in value, and said first and second bias voltage signals are at least as great in value as said nominal peak amplitude of said first and second oscillatory voltage signals, further comprising:

operatively coupling said first bias voltage signal to a non-inverting input of said first operational amplifier, and operatively coupling said second bias voltage signal to a non-inverting input of said second operational amplifier.

6. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 3, further comprising buffering a second node signal at said second node so as to form a buffered second node signal, wherein the operation of operatively coupling said second node through said first feedback resistor to said inverting input of said first operational amplifier comprises operatively coupling said buffered second node signal to a first terminal of said first feedback resistor, and operatively coupling a second terminal of said first feedback resistor to said inverting input of said first operational amplifier;

and buffering a third node signal at said third node so as to form a buffered third node signal, wherein the operation of operatively coupling said third node through said second feedback resistor to said inverting input of said second operational amplifier comprises operatively coupling said buffered third node signal to a first terminal of said second feedback resistor, and operatively coupling a second terminal of said second feedback resistor to said inverting input of said second operational amplifier.

7. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 6, wherein the operation of buffering said second node signal at said second node comprises operatively coupling said second node of said series circuit to a non-inverting input of a third operational amplifier;

and operatively coupling an inverting input of said third operational amplifier to an output of said third operational amplifier, wherein said buffered second node signal is generated at said output of said third operational amplifier; and

the operation of buffering said second node signal at said third node comprises operatively coupling said third node of said series circuit to a non-inverting input of a fourth operational amplifier; and

operatively coupling an inverting input of said fourth operational amplifier to an output of said fourth operational amplifier, wherein said buffered third node signal is generated at said output of said fourth operational amplifier.

8. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein said first complementary voltage signal comprises a first bias voltage signal, said second complementary voltage signal comprises a second bias voltage signal, said first and second bias voltage signals are substantially equal in value, and said first and second bias voltage signals are at least as great in value as said nominal peak amplitude of said first and second oscillatory voltage signals.

9. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 8, wherein said first and second bias voltage signals are each substantially constant.

10. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising at least one of selectively shunting a signal around said first sense resistor, wherein a frequency of said signal shunted around said first sense resistor is different from a frequency of said first or second oscillatory voltage signal, and selectively shunting a signal around said second sense resistor, wherein a frequency of said signal shunted around said second sense resistor is different from said frequency of said first or second oscillatory voltage signal.

11. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein the operation of generating said output signal further comprises generating an output signal responsive to a test signal, and said test signal provides for simulating a condition of the circuit element.

12. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising band-pass filtering said output signal from said operational amplifier, wherein a frequency range of a pass-band of said band-pass filter is adjusted responsive to an operating frequency of said first and second oscillatory voltage signals.

13. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising demodulating said output signal, or a signal responsive thereto, so as to generate at least one of a first in-phase signal component and a first quadrature phase signal component thereof, wherein said first in-phase signal component is in-phase with said first or second oscillatory voltage signal, and said first quadrature phase signal component is substantially 90 degrees out-of-phase with respect to said first or second oscillatory voltage signal

14. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 13, further comprising at least one of filtering said first in-phase output signal with a band-pass filter so as to generate a second in-phase output signal, and filtering said first quadrature-phase output signal with a band-pass filter so as to generate a second quadrature-phase output signal

15. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein further comprising detecting is a magnitude of said output signal, or said signal responsive thereto, is greater than a threshold, and indicating an error condition if said magnitude of said output signal, or said signal responsive thereto, is greater than said threshold.

16. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein said circuit element comprises at least one inductance coil.

17. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 16, further comprising operatively coupling said at least one inductance coil to a magnetic circuit of a vehicle;

and detecting a perturbation of said magnetic circuit responsive to said output signal.

18. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 17, wherein the operation of detecting a perturbation of said magnetic circuit comprises detecting a crash of said vehicle, wherein said perturbation of said magnetic circuit is responsive to said crash.

19. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 18, further comprising controlling a safety restraint system responsive to said output signal.

20. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 19, further comprising:

a. demodulating said output signal, or a signal responsive thereto, so as to generate at least one of a first in-phase signal component and a first quadrature phase signal component thereof, wherein said first in-phase signal component is in-phase with said first or second oscillatory voltage signal, and said first quadrature phase signal component is substantially 90 degrees out-of-phase with respect to said first or second oscillatory voltage signal; and

b. controlling a safety restraint actuator responsive to at least one of said first in-phase output signal, said first quadrature-phase output signal.

21. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 20, further comprising controlling a safety restraint actuator responsive to at least said first in-phase output signal.

22. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising:

c. detecting a signal responsive to a DC bias current in said series circuit; and

d. controlling at least one of said first and second complementary voltage signals so as to substantially null said signal responsive to said DC bias current in said series circuit.

23. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 22, wherein said first complementary voltage signal comprises a first bias voltage signal, said second complementary voltage signal comprises a second bias voltage signal, said first and second bias voltage signals are substantially equal in value, and said first and second bias voltage signals are at least as great in value as said nominal peak amplitude of said first and second oscillatory voltage signals.

24. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 23, wherein said first and second bias voltage signals are each substantially constant.

25. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 22, further comprising at least one of selectively shunting a signal around said first sense resistor, wherein a frequency of said signal shunted around said first sense resistor is different from a frequency of said first or second oscillatory voltage signal, and selectively shunting a signal around said second sense resistor, wherein a frequency of said signal shunted around said second sense resistor is different from said frequency of said first or second oscillatory voltage signal.