Method for monitoring stress-induced degradation of conductive interconnects

• US 20080107149A1
• Filed: 12/19/2007
• Published: 05/08/2008
• Est. Priority Date: 11/04/2005
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Andrew Cowley, Baozhen Li, Birendra Agarwala, Chih-Chao Yang, Du Nguyen, Hazara Rathore, Jason Gill, Kaushik Chanda, Lawrence Clevenger, Paul Mclaughlin, Ronald Filippi, Timothy Sullivan, Tom Lee
• Inventors: Sullivan, Timothy, Gill, Jason, Yang, Chih-Chao, McLaughlin, Paul, Li, Baozhen, Chanda, Kaushik, Agarwala, Birendra, Nguyen, Du, Clevenger, Lawrence, Rathore, Hazara, Lee, Tom, Filippi, Ronald, Cowley, Andrew
• Granted Patent: US 7,639,032 B2
• Time in Patent Office: Days
• US Class Current: 374/57
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

Claims

1. A method of testing an ability of a microelectronic element having conductive interconnects to withstand thermal stress, comprising:

providing an interconnect test structure within said microelectronic element, said interconnect test structure including;

i) a conductive metallic plate having an upper surface, a lower surface opposite said upper surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction transverse to said width and a thickness in a vertical direction extending between said upper surface and said lower surface, ii) a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end, and iii) an upper metallic via in at least substantial vertical alignment with said lower conductive via such that a line extending in said vertical direction through said metallic plate intersects said upper metallic via and said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate;

maintaining said microelectronic element at an elevated temperature for a predetermined period of time;

taking a first measurement of at least one electrical characteristic of said interconnect test structure prior to an end of said predetermined period of time;

taking a second measurement of said at least one electrical characteristic of said interconnect test structure at a time not prior to an end of said predetermined period of time; and

comparing a difference between said first and second measurements to at least one failure criterion to determine whether said microelectronic element passes or fails.

2. The method as claimed in claim 1, wherein said microelectronic element includes an integrated circuit containing active semiconductor devices, said microelectronic element including a plurality of said interconnect test structures, wherein said step of making said first measurement includes measuring said at least one electrical characteristic of each of said plurality of interconnect test structures, said step of making said second measurement includes measuring said at least one electrical characteristic of each of said plurality of interconnect test structures and said step of comparing is performed relative to said first and second measurements of said at least one electrical characteristic of each of said interconnect test structures.

3. The method as claimed in claim 2, wherein said at least one electrical characteristic includes resistance, wherein said failure criterion includes an increase in said resistance by a predetermined amount.

4. The method as claimed in claim 2, wherein said at least one electrical characteristic includes leakage current, wherein said failure criterion includes an increase in said leakage current by a predetermined amount.

5. The method as claimed in claim 1, wherein said bottom end of said upper metallic via contacts said metallic plate, and said interconnect test structure further includes an upper metallic line element in contact with said top end of said upper metallic via, wherein said line intersects said upper metallic line.

6. The method as claimed in claim 1, wherein said interconnect test structure further includes a lower element consisting essentially of at least one of conductive material or semiconductive material in contact with said bottom end of said lower via, wherein said line intersects said lower element.

7. The method as claimed in claim 1, wherein said interconnect test structure further includes a metallic connecting line, said metallic connecting line having an upper surface at least substantially level with said upper surface of said metallic plate, an inner end connected to said metallic plate, and an outer end horizontally displaced from at least one of said plurality of peripheral edges, said metallic connecting line having a width much smaller than said width of said at least one of said peripheral edges and a length greater than a width of said microelectronic element, wherein said bottom end of said upper metallic via contacts said metallic connecting line.

8. The method as claimed in claim 2, wherein at least particular ones of said plurality of interconnect test structures fail in relation to said failure criterion, said method further comprising evaluating said characteristics of said particular failing ones to determine whether said microelectronic element passes or fails.

9. The method as claimed in claim 2, wherein said microelectronic element includes a plurality of said integrated circuits attached to each other in a semiconductor substrate, said interconnect test structures being disposed in at least some of said plurality of integrated circuits, wherein said at least some integrated circuits include at least a first integrated circuit of said plurality of integrated circuits disposed adjacent to an edge of said semiconductor substrate and at least a second integrated circuit disposed near a center of said semiconductor substrate.

10. The method as claimed in claim 1, wherein said step of maintaining said microelectronic element at said elevated temperature includes maintaining said microelectronic element at a temperature corresponding to a maximum stress due to thermal expansion mismatch and vacancy-related diffusion.

11. The method as claimed in claim 10, wherein at least said metallic plate and said upper metallic via consist essentially of at least one metal selected from the group consisting of copper (Cu), aluminum (Al), gold (Au), and silver (Ag), wherein said microelectronic element is maintained at a temperature of 225 degrees centigrade.

12. The method as claimed in claim 10, wherein at least said metallic plate and said upper metallic via consist essentially of at least one metal selected from the group consisting of copper (Cu), aluminum (Al), gold (Au), and silver (Ag), wherein said step of maintaining said microelectronic element includes maintaining said microelectronic element at temperatures of 175 degrees centigrade, 225 degrees centigrade and 275 degrees centigrade.