DIGITAL RECEIVER FOR RADIO-FREQUENCY SIGNALS

• US 20080107213A1
• Filed: 12/28/2007
• Published: 05/08/2008
• Est. Priority Date: 06/14/2006
• Status: Active Grant

• Current Assignee: Hypres, Inc.
• Original Assignee: Hypres, Inc.
• Inventors: Gupta, Deepnarayan, Mukhanov, Oleg
• Granted Patent: US 7,991,013 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H03K 17/92 by the use, as active elements, of superconductive devices
• CPC Class Codes: H04B 1/005 adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A system and method for receiving radio frequency signals, comprising a plurality of analog signal couplers, for communicating a representation of a radio frequency signal; a respective analog to digital converter for each of said couplers, each having an output presenting a digital representation of the representation and an associated clock; a non-blocking switch matrix, receiving the plurality of outputs and associated clocks, and producing a plurality of regenerated outputs and associated regenerated clocks under selective control of a switch matrix signal; and a plurality of digital radio frequency signal processors, adapted to receive at least one regenerated output from the non-blocking switch matrix and associated regenerated clock.

Claims

1. A radio frequency receiver, comprising:

a plurality of analog signal couplers, for communicating a representation of a radio frequency signal;

a respective analog to digital converter for each of said couplers, each having an output presenting a digital representation of the representation and an associated clock;

a non-blocking switch matrix, receiving the plurality of outputs and associated clocks, and producing a plurality of regenerated outputs and associated regenerated clocks under selective control of a switch matrix signal; and

a plurality of digital radio frequency signal processors, adapted to receive at least one regenerated output from the non-blocking switch matrix and associated regenerated clock.

2. The receiver according to claim 1, wherein the associated clock for at least two of the respective analog to digital converters is independent.

3. The receiver according to claim 1, wherein the associated clock for a respective analog to digital converter operates above a Nyquist rate for a radio frequency carrier of the radio frequency signal.

4. The receiver according to claim 1, wherein each analog signal coupler is adapted to couple a radio frequency signal within a band, the band having an upper range limit, the associated clock for the respective analog to digital converter operating above a Nyquist rate for the upper range limit.

5. The receiver according to claim 1, wherein each analog signal coupler is adapted to couple a radio frequency signal within a band, the radio frequency signal comprising an information signal, the associated clock for the respective analog to digital converter operating above a minimum rate required to capture and digitally represent the information signal from the radio frequency signal.

6. The receiver according to claim 1, wherein at least two of said plurality of analog signal couplers are adapted to couple analog signals having information signals modulated on different radio frequency bands, said non-blocking switch matrix routing and regenerating a respective digital representation of the information signals to respective different digital radio frequency signal processors which are adapted to demodulate the respective information signal.

7. The receiver according to claim 1, wherein the digital representation is an oversampled discrete representation of the respective radio frequency signal.

8. The receiver according to claim 1, wherein at least one of said analog to digital converter, said non-blocking switch matrix, and said digital radio frequency processor comprises a plurality of superconducting elements operating at cryogenic temperatures.

9. The receiver according to claim 1, wherein said non-blocking switch matrix is adapted to simultaneously multicast the regenerated output and associated regenerated clock from a single output and associated clock for processing by at least two of the plurality of digital radio frequency signal processors.

10. The receiver according to claim 1, wherein at least one of said respective analog to digital converters generates a parallel multiple binary bit digital representation of the representation of the radio frequency signal, said parallel multiple binary bit digital representation and associated clock being routed by said non-blocking switch matrix to at least one digital radio frequency signal processor.

11. The receiver according to claim 1, wherein the regenerated output and associated regenerated clock are routed together to maintain proper synchronization at a radio frequency signal processor.

12. The receiver according to claim 1, further comprising a delay compensation network adapted to maintain proper synchronization among a plurality of data paths, each data path communicating a regenerated output and a respective regenerated clock.

13. The receiver according to claim 1, wherein said non-blocking switch matrix is adapted to simultaneously distribute a plurality of regenerated outputs with respective associated regenerated clocks, the plurality of associated regenerated clocks having respectively different clock frequencies.

14. The receiver according to claim 1, wherein said non-blocking switch matrix comprises a Banyan network.

15. The receiver according to claim 1, wherein the non-blocking switch matrix comprises a plurality of switch elements each controlled by at least one digital control line, to provide a digitally controllable input to output relationship, wherein a respective digital control line is applied to said switch elements in parallel.

16. The receiver according to claim 1, wherein the non-blocking switch matrix comprises a plurality of switches each controlled by at least one digital control line, to provide a digitally controllable input to output relationship, wherein a respective digital control line is applied to a first element, and the first element generates a signal which serves as an input to a second element, the first and second elements controlling respective switches.

17. The receiver according to claim 1, wherein the non-blocking switch matrix comprises a plurality of switches each controlled by at least one digital control line, to provide a digitally controllable input to output relationship between a respective analog signal coupler and a respective digital radio frequency signal processor, wherein a respective digital control line is applied to a plurality of first elements, which generate a state of a respective digital control line for control of at least one second element, the first and second elements controlling respective switches.

18. The receiver according to claim 1, wherein the radio frequency signals communicated through a respective plurality of radio frequency couplers are received through separate antennas serving separate bands.

19. The receiver according to claim 1, wherein a plurality of radio frequency signals are received through different antennas and communicated through a respective plurality of radio frequency couplers, and selectively concurrently routed through said non-blocking switch matrix to a plurality of digital channelizing receivers.

20. The receiver according to claim 1, wherein at least one digital radio frequency signal processor comprises a channelizing receiver implementing at least one stage of digital down-conversion of the digital representation from a frequency of the radio frequency signal to a lower frequency, while substantially retaining information modulated in a channel of the radio frequency signal.

21. The receiver according to claim 1, wherein at least one digital radio frequency signal processor comprises an channelizing receiver implementing at least one stage of digital down-conversion of the digital representation from a frequency of the radio frequency signal to a lower frequency, while substantially retaining in-phase and quadrature-phase information modulated in a channel of the radio frequency signal.

22. A system for receiving signals, comprising:

a plurality of signal receivers, adapted to generate digital data directly from a received radio frequency signal substantially without frequency translation, based on a digital data clock signal defined independently of the received signal and having a sufficiently high clock rate to preserve information modulated in the received radio frequency signal, each having a respective output; and

a switch matrix adapted to receive and selectively direct the outputs of the plurality of signal receivers, and respective associated digital data clock signals, to a plurality of digital signal processors, each accepting the generated digital data at the high clock rate.

23. The system according to claim 22, wherein a quantity of digital signal processor is fewer than a quantity of signal receivers, and wherein the switch matrix provides a multicasting capability which permits an output of a respective signal receiver to be selectively provided to a plurality of digital signal processors.

24. The system according to claim 22, wherein a plurality of channels of the switch matrix have independently tunable analog delay.

25. A radio frequency receiver method, comprising:

converting an analog representation of each of a plurality of radio frequency signals to a respective plurality of digital signals with a respective analog to digital converter, each respective analog to digital converter having an output presenting a digital representation of the analog representation and an associated clock;

receiving the plurality of outputs and associated clocks with a non-blocking switch matrix, and producing a plurality of regenerated outputs and associated regenerated clocks under selective control of a switch matrix signal; and

receiving at least one regenerated output from the non-blocking switch matrix and associated regenerated clock with a plurality of digital radio frequency signal processors.

26. The method according to claim 25, wherein the associated clock for at least two of the respective analog to digital converters is independent.

27. The method according to claim 25, wherein the associated clock for a respective analog to digital converter operates above a Nyquist rate for a radio frequency carrier of the radio frequency signal.

28. The method according to claim 25, wherein each radio frequency signal is situated within a band, the band having an upper range limit, the associated clock for the respective analog to digital converter operating above a Nyquist rate for the upper range limit.

29. The method according to claim 25, wherein each radio frequency signal is situated within a band, the radio frequency signal comprising an information signal, the associated clock for the respective analog to digital converter operating above a minimum rate required to capture and digitally represent the information signal from the radio frequency signal.

30. The method according to claim 25, wherein at least two of the radio frequency signals comprise information signals modulated on different radio frequency bands, said non-blocking switch matrix routing and regenerating a respective digital representation of the information signals to respective different digital radio frequency signal processors which are adapted to demodulate the respective information signal.

31. The method according to claim 25, wherein the digital representation is an oversampled discrete representation of the respective radio frequency signal.

32. The method according to claim 25, wherein at least one of said analog to digital converter, said non-blocking switch matrix, and said digital radio frequency processor comprises a plurality of superconducting elements, further comprising the step of operating said at least one of said analog to digital converter, said non-blocking switch matrix, and said digital radio frequency processor at cryogenic temperatures.

33. The method according to claim 25, further comprising the step of simultaneously multicasting a single output and associated clock as the regenerated output and associated regenerated clock from said non-blocking switch matrix for processing by at least two of the plurality of digital radio frequency signal processors.

34. The method according to claim 25, wherein at least one of said respective analog to digital converters generates a parallel multiple binary bit digital representation of the representation of the radio frequency signal, said parallel multiple binary bit digital representation and associated clock being routed by said non-blocking switch matrix to at least one digital radio frequency signal processor.

35. The method according to claim 25, further comprising the step of routing the regenerated output and associated regenerated clock together to maintain proper synchronization at a radio frequency signal processor.

36. The method according to claim 25, further comprising delaying data traveling over at least one data path with a delay compensation network to maintain proper synchronization among a plurality of data paths, each data path communicating a regenerated output and a respective regenerated clock.

37. The method according to claim 25, further comprising the step of simultaneously distributing a plurality of regenerated outputs with respective associated regenerated clocks from said non-blocking switch matrix, the plurality of associated regenerated clocks having respectively different clock frequencies.

38. The method according to claim 25, wherein said non-blocking switch matrix comprises a Banyan network.

39. The method according to claim 25, wherein said non-blocking switch matrix comprises a plurality of switch elements each controlled by at least one digital control line, to provide a digitally controllable input to output relationship, further comprising the step of applying a signal over a respective digital control line to said switch elements in parallel.

40. The method according to claim 25, wherein said non-blocking switch matrix comprises a plurality of switches each controlled by at least one digital control line, to provide a digitally controllable input to output relationship, further comprising the step of applying a first signal through respective digital control line to a first element, and generating a second signal with said first element which serves as an input to a second element, said first and second elements controlling respective switches.

41. The method according to claim 25, wherein the non-blocking switch matrix comprises a plurality of switches each controlled by at least one digital control line, to provide a digitally controllable input to output relationship between a respective analog signal coupler and a respective digital radio frequency signal processor, further comprising the step of applying a signal over a respective digital control line to a plurality of first elements, which generates a state of a respective digital control line for control of at least one second element, the first and second elements controlling respective switches.

42. The method according to claim 25, further comprising the step of communicating the radio frequency signals through a respective plurality of radio frequency couplers, said respective radio frequency couplers receiving the radio frequency signals through separate antennas, serving separate bands corresponding to each coupler.

43. The method according to claim 25, further comprising the steps of receiving a plurality of radio frequency signals through different antennas and communicating the received radio frequency signals through a respective plurality of radio frequency couplers, and selectively concurrently routing said digital representation of the analog representation and an associated clock through said non-blocking switch matrix, said plurality of digital radio frequency signal processors comprising a plurality of digital channelizing receivers.

44. The method according to claim 25, wherein at least one digital radio frequency signal processor comprises a channelizing receiver implementing at least one stage of digital down-conversion of the digital representation from a frequency of the radio frequency signal to a lower frequency, while substantially retaining information modulated in a channel of the radio frequency signal.

45. The method according to claim 25, wherein at least one digital radio frequency signal processor comprises a channelizing receiver implementing at least one stage of digital down-conversion of the digital representation from a frequency of the radio frequency signal to a lower frequency, while substantially retaining in-phase and quadrature-phase information modulated in a channel of the radio frequency signal.

46. A method for receiving signals, comprising:

generating digital data directly from a received radio frequency signal substantially without frequency translation, based on a digital data clock signal defined independently of the received signal and having a sufficiently high clock rate to preserve information modulated in the received radio frequency signal, each having a respective output; and

receiving and selectively directing the outputs of the plurality of signal receivers and respective associated digital data clock signals with a non-blocking switch matrix, to a plurality of digital signal processors, each accepting the generated digital data at the high clock rate.

47. The method according to claim 46, wherein a quantity of digital signal processor is fewer than a quantity of signal receivers, and wherein the switch matrix provides a multicasting capability which permits an output of a respective signal receiver to be selectively provided to a plurality of digital signal processors.

48. The method according to claim 46, wherein a plurality of channels of the switch matrix have independently tunable analog delay.