RELEASE STRATEGIES FOR MAKING TRANSFERABLE SEMICONDUCTOR STRUCTURES, DEVICES AND DEVICE COMPONENTS

• US 20080108171A1
• Filed: 09/20/2007
• Published: 05/08/2008
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Board of Trustees of The University of Illinois
• Original Assignee: Board of Trustees of The University of Illinois
• Inventors: Menard, Etienne, Rogers, John, Ko, Heung Cho, Nuzzo, Ralph, Yoon, Jongseung, Meitl, Matthew, Baca, Alfred
• Granted Patent: US 7,932,123 B2
• Time in Patent Office: Days
• US Class Current: 438/73
• CPC Class Codes: B81C 1/0046 using stamping, e.g. imprinting nanoimprinting for making etch masks G03F7/0002
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 31/03046 including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/072 the potential barriers being only of the PN heterojunction type
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 31/184 : the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: H01L 31/1844 : comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: Y02E 10/52 : PV systems with concentrators
• CPC Class Codes: Y02E 10/544 : Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 156/1195 : Delaminating from release surface

Abstract

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Claims

1. A method for making a device or device component;

said method comprising the steps of;

providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers;

wherein at least a portion of said release layers are positioned between functional layers in said multilayer structure;

releasing at least a portion of said functional layers from said multilayer structure by separating one or more of said release layers or a portion thereof from one or more of said functional layers, thereby generating a plurality of transferable structures; and

printing one or more of said transferable structures onto a device substrate or device component supported by a device substrate, thereby making said device or said device component.

2. The method of claim 1 wherein said step of releasing at least a portion of said functional layers from said multilayer substructure comprises physically separating at least one pair of adjacent layers, wherein said pair of adjacent layers comprises a release layer positioned adjacent to a functional layer in said multilayer structure.

3. The method of claim 1 wherein said step of releasing at least a portion of said functional layers from said multilayer substructure comprises removing at least a portion of one or more of said release layers in said multilayer structure.

4. The method of claim 1 wherein said step of releasing at least a portion of said functional layers from said multilayer structure comprises separating one or more of said release layers or a portion thereof from one or more of said functional layers using a technique selected from the group consisting of:

etching one or more release layers;

thermally shocking one or more release layers;

ablating or decomposing one or more release layers by exposure of said release layers to electromagnetic radiation from a laser source; and

decomposing one or more release layers by contacting said release layers with a chemical agent.

5. The method of claim 1 wherein said functional layers are at least partially transparent to electromagnetic radiation from a laser source exposed to said multilayer structure, wherein said electromagnetic radiation is capable of ablating or decomposing at least a portion of said release layers, said method further comprising the step of exposing said multilayer structure to said electromagnetic radiation from said laser source, thereby ablating or decomposing at least a portion of one or more of said release layers.

6. The method of claim 5, wherein the multilayer structure is supported on a substrate and said electromagnetic radiation is at least partially transmitted through said substrate, thereby ablating or decomposing at least a portion of one or more of said release layers

7. The method of claim 1 wherein said step of releasing at least a portion of said functional layers from said multilayer substructure comprises the steps of:

introducing an interfacial crack into one or more of said release layers; and

mechanically stressing said release layers so as to cause propagation of said interfacial crack, thereby resulting in release of one or more functional layers.

8. The method of claim 7 wherein said crack is mechanically, chemically or thermally introduced into one or more of said release layers.

9. The method of claim 1 wherein said functional layers in said multilayer structure are released one at a time.

10. The method of claim 1 wherein more than one said functional layers in said multilayer structure are released simultaneously.

11. The method of claim 1 further comprising the step of providing a mask layer in physical contact with one or more functional layers, wherein said mask layer is capable of preventing exposure of one or more functional layers to an etchant, solvent or chemical agent provided to said multilayer structure during said step of releasing at least a portion of said functional layers from said multilayer structure.

12. The method of claim 1 further comprising the step of providing a carrier film in contact with one or more of said functional layers prior to said step of releasing at least a portion of said functional layers from said multilayer substructure.

13. The method of claim 1 further comprising the step of making recessed features in at least one of said functional layers so as to generate said transferable structures having one or more preselected microsized or nanosized physical dimensions.

14. The method of claim 13 wherein said step of generating recessed features in at least one of said functional layers is carried out using a patterning technique selected from the group consisting of photolithography, soft lithography, electron beam direct writing, and photoablation patterning methods.

15. The method of claim 1, wherein said step of printing one or more said transferable structures onto said device substrate or device component supported by said device substrate is carried out via contact printing.

16. The method of claim 15, wherein said step of printing one or more said transferable structures onto said device substrate or device component supported by said device substrate is carried out via a technique selected from the group consisting of dry transfer contact printing, soft lithographic microtransfer printing and soft lithographic nanotransfer printing.

17. The method of claim 16, wherein said step of printing transferable structure comprises contacting a target substrate with said functional layer and removing said target substrate from said functional layer, thereby transferring at least a portion of said functional layer from said multilayer structure to said target substrate.

18. The method of claim 16, wherein said step of printing transferable structure comprises contacting an elastomeric stamp with said functional layer and removing said elastomeric stamp from said functional layer, thereby transferring said functional layer from said multilayer structure to said elastomeric stamp.

19. The method of claim 1 wherein said step of printing one or more said transferable structures onto said device substrate or device component supported by said device substrate is carried out via:

solution printing

20. The method of claim 19 wherein said step of printing one or more said transferable structures onto said device substrate or device component supported by said device substrate is carried out via a technique selected from the group consisting of fluidic self assembly, ink jet printing, thermal transfer printing, and screen printing.

21. The method of claim 1 wherein at least one of said functional layers of said multilayer structure comprises a semiconductor layer or a sequence of semiconductor layers.

22. The method of claim 21 wherein said sequence of semiconductor layers comprises at least one semiconductor layer selected from the group consisting of:

a single crystalline semiconductor layer, an organic semiconductor layer, an inorganic semiconductor layer, a III-V semiconductor layer; and

a group IV elemental or compound semiconductor.

23. The method of claim 21 wherein said sequence of semiconductor layers comprises at least two semiconductor layers comprising different semiconductor materials.

24. The method of claim 1 wherein at least one of said functional layers of said multilayer structure comprises one or more dielectric layers or one or more conductor layers.

25. The method of claim 1 wherein said multilayer structure further comprises one or more carrier films provided in physical contact with one or more functional layers.

26. The method of claim 1 wherein at least one of said functional layers of said multilayer structure comprises an electronic, optical or electro-optic device or a component of an electronic, optical or electro-optic device.

27. The method of claim 26 wherein at least one of said functional layers of said multilayer structure comprises an electronic, optical or electro-optic device or a component of an electronic, optical or electro-optic device selected from the group consisting of:

a P—

N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.

28. The method of claim 1 further comprising the step of generating said multilayer structure on a substrate, wherein at least one release layer is provided between said functional layers and said substrate.

29. The method of claim 28 wherein said step of generating said multilayer structure on said substrate is carried out using a technique selected from the group consisting of:

vapor-phase epitaxy, molecular-beam epitaxy, evaporation deposition, metalorganic chemical vapor deposition, chemical vapor deposition, physical vapor deposition, sputtering deposition, sol-gel coating, electron beam evaporation deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, liquid phase epitaxy, electrochemical deposition, and spin coating.

30. The method of claim 28 further comprising the step of repeating said steps of generating said multilayer structure on a substrate, releasing at least a portion of said functional layers from said multilayer structure and printing one or more of said transferable structures;

wherein said substrate is reused during said step of repeating said steps of generating said multilayer structure on a substrate, releasing at least a portion of said functional layers from said multilayer structure and printing one or more of said transferable structures.

31. The method of claim 28 wherein at least a portion of said functional layers, release layers or both of said multilayer structure are thin films epitaxially grown on said substrate.

32. The method of claim 31 wherein said functional layers and release layers comprise a preselected sequence of thin films epitaxially grown on said substrate.

33. The method of claim 32 wherein said preselected sequence of thin films comprises alternating release layers and functional layers epitaxially grown on said substrate.

34. The method of claim 1 wherein said functional layers of said multilayer structure have thicknesses selected from the range of about 5 nm to about 50,000 nanometers.

35. The method of claim 1 wherein said multilayer structure comprises about 2 to about 200 functional layers.

36. The method of claim 1 wherein said multilayer structure comprises about 2 to about 200 release layers.

37. The method of claim 1 comprising a method of making a photovoltaic device or device array, a transistor device or device array, a light emitting diode device or device array, a laser or array of lasers, or a sensor or sensor array.

38. The method of claim 1 comprising a method of making an integrated electronic circuit, a microelectromechanical device or a nanoelectromechanical device.

39. A method of making transferable semiconductor structures;

said method comprising the steps of;

providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers;

wherein at least a portion of said release layers are positioned between functional layers in said multilayer structure, at least a portion of said functional layers comprising one or more semiconductor thin films; and

releasing at least a portion of said functional layers from said multilayer structure by separating one or more of said release layers or a portion thereof from one or more of said functional layers, thereby generating said transferable semiconductor structures.

40. The method of claim 39 further comprising further comprising the step of generating said multilayer structure on a substrate, wherein at least one release layer is provided between said functional layers and said substrate.

41. The method of claim 40 further comprising the step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said functional layers from said multilayer structure;

wherein said substrate is reused during said step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said functional layers from said multilayer structure.

42. A method for making a photovoltaic device or device array, said method comprising the steps of:

providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers;

wherein at least a portion of said release layers are positioned between functional layers in said multilayer structure, at least a portion of said functional layers comprising photovoltaic cells;

releasing at least a portion of said functional layers from said multilayer structure by separating one or more of said release layers or a portion thereof from one or more of said functional layers, thereby generating a plurality of transferable photovoltaic cells; and

printing one or more of said transferable photovoltaic cells onto a device substrate or device component supported by a device substrate by contact printing or solution printing, thereby making said electronic device or said electronic device component.

43. The method of claim 42 wherein said photovoltaic cells of said functional layers comprise a preselected sequence of semiconductor thin films.

44. The method of claim 43 further comprising the step of making recessed features in at least one of said functional layers so as to generate said transferable photovoltaic cells having one or more preselected microsized or nanosized physical dimensions.

45. A method for making a device or device component, said method comprising the steps of:

providing a sacrificial layer on at least a portion of a substrate surface, said sacrificial layer having a receiving surface;

patterning said sacrificial layer to generate a pattern of exposed substrate surface;

depositing a functional layer on at least a portion of said sacrificial layer receiving surface and exposed substrate surface pattern, thereby generating one or more functional layer anchors corresponding to said pattern of exposed substrate; and

releasing at least a portion of said functional layer, wherein the pattern of functional layer anchors remain at least partially anchored to said substrate and at least a portion of said functional layer not anchored to said substrate is released, thereby generating a plurality of transferable structures.

46. The method of claim 45, further comprising printing one or more of said transferable structures onto a device substrate or device component supported by a device substrate.

47. The method of claim 46, wherein the releasing step comprises:

contacting an elastomeric stamp to at least a portion of said functional layer; and

removing said stamp from contact with said functional layer, thereby removing at least a portion of said functional layer that is not anchored to said substrate.

48. The method of claim 46, wherein the releasing step comprises:

contacting said device substrate surface to at least a portion of said functional layer; and

removing said device substrate surface from contact with said functional layer, thereby transferring at least a portion of said functional layer that is not anchored to said substrate to said device substrate or device component supported by said device substrate surface.

49. The method of claim 45, wherein the releasing step uses a technique selected from the group consisting of:

etching said sacrificial layer;

thermally shocking said sacrificial layer;

ablating or decomposing by exposure of said sacrificial layer to radiation from a laser source; and

decomposing said sacrificial layer by contacting said sacrificial layer with a chemical agent.

50. The method of claim 45, wherein said functional layer is part of a multilayer structure.

51. A method for fabricating a plurality of transferable semiconductor elements provided in a multilayer array, said method comprising the steps of:

providing a wafer having an external surface, said wafer comprising an inorganic semiconductor;

masking selected regions of said external surface by providing a first mask to said external surface, thereby generating masked regions and unmasked regions of said external surface of said wafer;

etching said unmasked regions of said external surface of said wafer, thereby generating a plurality of relief features extending from said external surface into said wafer, wherein at least a portion of said relief features each have at least one contoured side surface having a contour profile that varies spatially along the length of said at least one side;

masking said contoured side surfaces by providing a second mask, wherein said contoured side surface are only partially masked by said second mask, thereby generating masked and unmasked regions provided along the length of said side surfaces; and

etching said unmasked regions of side surfaces;

thereby generating said plurality of transferable semiconductor elements provided in said multilayer array.

52. The method of claim 51 wherein said wafer is a bulk semiconductor wafer.

53. The method of claim 51 wherein said wafer is a silicon wafer having a (111) orientation.

54. The method of claim 51 wherein said step of etching said unmasked regions of said external surface of said wafer is carried out by cyclic exposure of the side surfaces of said recessed features to etchants and etch resist materials.

55. The method of claim 54 wherein said etching step is carried out by cyclic exposure of the side surfaces of said recessed features to reactive ion etchants and etch resist materials.

56. The method of claim 54 wherein said etching step is carried out using Inductively Coupled Plasma Reactive Ion Etching, Buffered Oxide Etchant or a combination of both Inductively Coupled Plasma Reactive Ion Etching and Buffered Oxide Etchant etching techniques.

57. The method of claim 51 wherein said contour profiles of said contoured side surfaces have a plurality of features extending lengths that intersect a longitudinal axis of the lengths of said side surfaces.

58. The method of claim 57 wherein said features of said contour profiles are selected from the group consisting of ridges, ripples and scalloped shaped recessed features provided on said side surfaces.

59. The method of claim 56, wherein said ridges, ripples or scalloped shaped recessed features function as shadow masks during said step of masking said contoured side surfaces by providing said second mask, thereby generating said unmasked regions of said side surfaces.

60. The method of claim 51 wherein said step of masking said contoured side surfaces by providing a second mask is carried out via angled vapor deposition of a mask material.

61. The method of claim 51 wherein said step of etching said unmasked regions of side surfaces is carried out via anisotropic etching.

62. The method of claim 61 wherein said wafer is a silicon wafer having an (111) orientation, and wherein said step of etching said unmasked regions of side surfaces is carried out via anisotropic etching preferentially along <

110>

directions of said silicon wafer.

63. The method of claim 61 wherein said anisotropic etching is provided by exposing said unmasked regions of said side surface to a strong base.

64. The method of claim 51 wherein said etching step of said unmasked regions of side surfaces generates said transferable semiconductor elements, wherein each of said elements are connected to said wafer via a bridge element.

65. The method of claim 51 wherein said first mask, said second mask or both is an etch resistant mask.

66. A method of assembling a plurality transferable semiconductor elements on a substrate, said method comprising the steps of:

providing said plurality of transferable semiconductor elements provided in a multilayer array of claim 51;

printing said transferable semiconductor elements on said substrate.

67. A method of making an electronic device or component of an electronic device, said method comprising the steps of:

providing said plurality of transferable semiconductor elements provided in a multilayer array of claim 51;

printing said transferable semiconductor elements on a substrate, thereby making said electronic device or component of said electronic device.

68. The method of claim 66, wherein said printing step is carried out by contact printing.

69. The method of claim 66, wherein said printing step is sequentially printing transferable semiconductor in different layers of said multilayer.

70. The method of claim 69, wherein printing semiconductor elements in a first layer of said array expose one or more transferable semiconductor elements in a layer of said array positioned underneath said first layer.

71. A method of making a transferable semiconductor element anchored to a substrate, said method comprising:

generating said transferable semiconductor element supported by an external surface of said substrate;

providing a heterogeneous anchor element in physical contact with said transferable semiconductor element and in physical contact with said substrate or a structure provided thereon, thereby anchoring said semiconductor element to said substrate.

72. The method of claim 71 wherein said step of providing said heterogeneous anchor element comprises depositing or coating a layer of material that covers a portion of said substrate.

73. The method of claim 72 wherein said layer covers a portion of said external surface of said substrate.

74. The method of claim 72 wherein said step of generating said transferable semiconductor element exposes one or more exposed regions of said external surface or structure provided thereon, wherein said step of providing said heterogeneous anchor element comprises depositing or coating said layer on at least a portion of said exposed regions of said external surface or structure provided thereon.

75. The method of claim 72 wherein said layer of material comprises a thin film structure.

76. The method of claim 72 wherein said layer of material comprises a resist material.

77. The method of claim 72 wherein said layer of material comprises SiN or PECVD dielectric.

78. The method of claim 72 wherein said layer of material is provided in contact with and extends along a side of said transferable semiconductor element, wherein said layer of material terminates in and contacts said external surface of said substrate or structure provided thereon.

79. The method of claim 78 wherein said layer of material comprises a post structure that connects a side of said transferable semiconductor element to said external surface of said substrate or structure provided thereon.

80. The method of claim 71 wherein said transferable semiconductor element comprises a single semiconductor layer.

81. The method of claim 71 wherein said transferable semiconductor element comprises a multilayer structure having a plurality of semiconductor layers.

82. The method of claim 71 wherein said step of generating said transferable semiconductor element comprises providing a multilevel array of transferable semiconductor elements supported by an external surface of said substrate;

wherein said step of providing said heterogeneous anchor element comprises depositing or coating a layer of material that contacts the sides of said transferable semiconductor elements in said multilayer array and contacts a portion of said external surface of said substrate or structure provided thereon.

83. The method of claim 71 wherein said heterogeneous anchor element functions as an etch stop layer.

84. A method of assembling a transferable semiconductor element, said method comprising the steps of:

providing the transferable semiconductor element anchored to said substrate of claim 71;

transferring said transferable semiconductor element onto a device substrate by printing.

85. The method of claim 84 wherein said step of transferring said transferable semiconductor element onto said device substrate by printing is carried out by contact printing.

86. The method of claim 84 wherein said step of transferring said transferable semiconductor element onto said device substrate by printing is carried out by the steps of:

contacting said transferable semiconductor element with a transfer device having a contact surface, wherein contact between said contact surface and said transferable semiconductor element binds said transferable semiconductor element to said contact surface;

moving said transfer device in a manner resulting in fracture of said heterogeneous anchoring element, thereby transferring said transferable semiconductor structure from said substrate to said transfer device, thereby forming said contact surface having said transferable semiconductor element disposed thereon;

contacting said transferable semiconductor element disposed on said contact surface with a receiving surface of said device substrate; and

separating said contact surface of said conformable transfer device and said transferable semiconductor element, wherein said transferable semiconductor element is transferred onto said receiving surface, thereby assembling said transferable semiconductor element on said receiving surface of said substrate.

87. A method of making a device, said method comprising the steps of:

providing the transferable semiconductor element anchored to said substrate of claim 71;

transferring said transferable semiconductor element onto a device substrate by printing.

88. The method of claim 87 wherein said step of transferring said transferable semiconductor element onto said device substrate by printing is carried out by contact printing.

89. The method of claim 88 wherein said step of transferring said transferable semiconductor element onto said device substrate by printing is carried out by the steps of:

contacting said transferable semiconductor element with a transfer device having a contact surface, wherein contact between said contact surface and said transferable semiconductor element binds said transferable semiconductor element to said contact surface;

moving said transfer device in a manner resulting in fracture of said heterogeneous anchoring element, thereby transferring said transferable semiconductor structure from said substrate to said transfer device, thereby forming said contact surface having said transferable semiconductor element disposed thereon;

contacting said transferable semiconductor element disposed on said contact surface with a receiving surface of said device substrate; and

separating said contact surface of said conformable transfer device and said transferable semiconductor element, wherein said transferable semiconductor element is transferred onto said receiving surface, thereby assembling said transferable semiconductor element on said receiving surface of said substrate.

90. A method for generating a multilayer array of transferable semiconductor elements, said method comprising the steps of:

providing a substrate having an external surface;

providing a multilayer structure supported by said external surface of said substrate, wherein said multilayer structure comprises an alternating sequence of semiconductor layers and sacrificial layers;

generating one or more recess features by removing material from said multilayer structure; and

depositing or coating a heterogeneous anchor element in said one or more recess features, thereby anchoring at least a portion of each of said semiconductor layers to said substrate external surface, or one or more semiconductor layers beneath a semiconductor top-layer of said multilayer structure, or both.

91. The method of claim 90, wherein said recess feature traverses from a top layer of said multilayer structure to said substrate external surface thereby exposing regions of said substrate external surface, and said heterogeneous anchor element anchors each of said semiconductor layers to said substrate external surface.

92. The method of claim 90, wherein said recess feature traverses from a first semiconductor top layer of said multilayer structure to a second semiconductor layer beneath said top-layer, and said heterogeneous anchor element anchors said first semiconductor layer to said second semiconductor layer.

93. The method of claim 90 wherein said depositing or coating step is carried out using a technique selected from the group consisting of:

vapor-phase epitaxy, molecular-beam epitaxy, evaporation deposition, metalorganic chemical vapor deposition, chemical vapor deposition, physical vapor deposition, sputtering deposition, sol-gel coating, electron beam evaporation deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, liquid phase epitaxy, electrochemical deposition, and spin coating.

94. The method of claim 92, further comprising:

selectively removing said sacrificial layer that is beneath said first semiconductor top-layer;

releasing said first semiconductor top layer;

removing said anchor element,

and repeating said generating and depositing steps, thereby anchoring said second semiconductor layer to a third semiconductor layer that is beneath said second semiconductor layer.

95. The method of claim 94, wherein the process is repeated until all the semiconductor layers are removed from said substrate external surface.

96. The method of claim 95, wherein said substrate comprises a wafer, and said substrate is reused to support a second multilayer structure.

97. The method of claim 91 further comprising:

removing said sacrificial layers;

releasing said semiconductor layers;

removing said anchor elements; and

reusing said substrate by providing a second multilayer structure supported by said external surface of said substrate and repeating said steps for generating an anchor that anchors each of said semiconductor layers to said substrate external surface.