METHOD OF FORMING AN INTEGRATED CIRCUIT INCLUDING A TRANSISTOR

• US 20080108199A1
• Filed: 12/21/2007
• Published: 05/08/2008
• Est. Priority Date: 06/29/2004
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schwerin, Ulrike
• Application Number:
  US11/963,044
• Publication Number:
  US 20080108199A1
• Time in Patent Office: Days
• US Class Current: 438/364
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

A method of forming an integrated circuit including a transistor is disclosed. One embodiment provides an active zone formed in a semiconductor substrate. Trench insulator structures and cell insulator structures are adjacent to the active zone. A gate electrode is formed including a buried portion. The buried portion is formed in a self-aligned manner with respect to the cell insulator structures.

Claims

1. A method of forming an integrated circuit including a transistor, comprising:

forming an active zone in a semiconductor substrate, trench insulator structures and cell insulator structures being adjacent to the active zone; and

forming a gate electrode including a buried portion,

wherein the buried portion is formed in a self-aligned manner with respect to the cell insulator structures.

2. The method of claim 1, wherein the buried portion of the gate electrode comprises plate sections adjacent to a body region of the transistor.

3. The method of claim 2, wherein forming the plate sections comprises filling a conductive material into pockets formed in the cell insulator structures.

4. The method of claim 1, comprising forming the buried portion of the gate electrode in part in a gate trench that is etched into the active zone and extends between two opposing trench insulator structures facing each other at the active zone.

5. A method of forming an integrated circuit including a transistor, the method comprising:

forming an active zone in a semiconductor substrate between two opposing trench insulator structures and two opposing cell insulator structures;

covering the active zone with a section of a protective layer;

etching the protective layer to expose sections of the active zones adjacent to the cell insulator structures, wherein a central portion of the active zone remains covered;

applying a hole mask material to cover the exposed sections of the active zone;

removing the section of the protective layer to expose the central portion;

etching the material of the trench insulator structures to provide pockets adjacent to the active zone; and

filling the pockets with a conductive material to form a gate electrode.

6. The method of claim 5, wherein the trench insulator structures and the cell insulator structures are protruding over the active zone, and further comprising:

removing an upper portion of the cell insulator structures after providing the section of the protective layer.

7. A method of forming an integrated circuit including a transistor comprising:

forming an active zone in a semiconductor substrate, between two opposing trench insulator structures and between two opposing cell insulator structures being adjacent to the active zone;

covering the active zone with a section of a protective layer;

etching the protective layer to expose sections of the active zones adjacent to the cell insulator structures, wherein a central portion of the active zone remains covered by the section of the protective layer;

forming a hole mask material to cover the exposed sections of the active zone;

removing the section of the protective layer to uncover the central portion of the active zone;

etching the uncovered portion of the active zone to form a gate trench; and

filling the gate trench with a conductive material to form a gate electrode.

8. The method of claim 7, wherein the trench insulator structures and the cell insulator structures are protruding over the active zone, and further comprising:

removing an upper portion of the cell insulator structures after providing the section of the protective layer.

9. The method of claim 7, further comprising:

etching the trench insulator structures after etching the uncovered portion of the active zone.

10. The method of claim 9, comprising etching the trench insulator structures isotropically.

11. A method for fabricating an integrated circuit including transistors, the method comprising:

introducing cell insulator structures and strip-like, parallel trench insulator structures into a semiconductor substrate to form cell rows spaced apart from one another by one of the trench insulator structures respectively and, within each of the cell rows, a plurality of semiconductor fins from the semiconductor substrate, the semiconductor fins spaced apart from one another by one of the cell insulator structures;

providing a hole mask that covers the trench insulator structures and at least outer mask sections of the semiconductor fins adjoining the cell insulator structures and that comprises openings exposing trench sections of the semiconductor fins;

uncovering and pulling back sections of the trench insulator structures that adjoin the trench sections of the semiconductor fins to form pockets in the trench insulator structures on both sides in a manner adjoining the trench sections; and

filling the pockets with conductive material to form gate conductor structures, wherein each gate conductor structure surrounds one of the semiconductor fins on three sides in the region of the trench sections.

12. The method of claim 11, comprising uncovering through the openings in the hole mask the trench sections in each case from one adjoining trench insulator structure as far as the opposite adjoining trench insulator structure.

13. The method of claim 11, comprising effecting the uncovering of sections of the trench insulator structures by introducing gate trenches into the semiconductor fins using the hole mask.

14. The method of claim 11, comprising:

providing the hole mask and the trench insulator structures from materials which can be jointly etched selectively with respect to the semiconductor substrate; and

effecting the uncovering of the sections of the trench insulator structures and the pulling back of the uncovered sections simultaneously in the course of an etching process with a high isotropic portion.

15. The method of claim 14, comprising providing the trench insulator structures and the hole mask from the same material.

16. The method of claim 14, comprising effecting the pulling back via a wet etching.

17. The method of claim 11, wherein providing the hole mask comprises:

applying a protective layer to the semiconductor substrate prior to the introduction of the trench insulator structures and the cell insulator structures, the protective layer being provided from a different material than the trench insulator structures;

applying an auxiliary layer;

photolithographically patterning the auxiliary layer to form from the auxiliary layer an auxiliary mask with strip-like trenches running orthogonally with respect to the cell rows and to uncover the protective layer in the projection of the trench sections of the semiconductor fins; and

pulling back the protective layer selectively with respect to the material of the trench insulator structures, to form the hole mask in sections from residual sections of the protective layer, the trench insulator structures and the cell insulator structures.

18. The method of claim 17, comprising wherein in each case precisely one trench section of the respective semiconductor fin that is formed between the two outer mask sections is uncovered through one of the openings in the hole mask.

19. The method of claim 17, comprising wherein in each case two trench sections of the respective semiconductor fin that are formed in each case between one of the mask sections and a central mask section are uncovered through two of the openings in the hole mask.

20. The method of claim 11, comprising providing the semiconductor fins in each case with precisely one trench section and the two mask sections, wherein providing the hole mask comprises:

applying a protective layer to the semiconductor substrate prior to introducing the trench insulator structures and the cell insulator structures, wherein the protective layer is provided from a different material than the trench insulator structures and the cell insulator structures;

providing the trench insulator structures and the cell insulator structures from different materials;

pulling back the cell insulator structures selectively with respect to the material of the protective layer and the material of the trench insulator structures;

isotropically pulling back the protective layer, wherein the trench sections of the semiconductor fins remain covered by sections of the pulled-back protective layer and wherein the two mask sections of the semiconductor fins that adjoin the cell insulator structures are uncovered;

applying the material of the hole mask;

planarizing and removing the material of the hole mask at least as far as the upper edge of the sections of the pulled-back protective layer; and

removing the sections of the pulled-back protective layer selectively with respect to the material of the hole mask.

21. The method of claim 11, comprising:

providing the cell insulator structures within the cell rows in each case at the spacing of a cell length; and

forming the semiconductor fins of mutually adjacent cell rows in a manner offset by in each case half a cell length with respect to one another.

22. The method of claim 11, comprising forming in each case the cell insulator structures as a filling of an upper section of a hole trench, in the lower section of which a trench capacitor is formed.