HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE

• US 20080108212A1
• Filed: 10/19/2006
• Published: 05/08/2008
• Est. Priority Date: 10/19/2006
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bowman, Lee A., Schwantes, Stefan, Miller, Gayle W., Moss, Thomas S.
• Application Number:
  US11/550,964
• Publication Number:
  US 20080108212A1
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Apparatus and a method for adding non-volatile memory cells with trench-filled vertical gates to conventional MOSFET surface devices that have their drain and source regions horizontally positioned near the top surface of a substrate. A surface MOSFET device is used as a structural platform to which is added a vertical trench-filled polysilicon gate and a word line region using a small number of additional mask layers and fabrication process modifications. A vertical trench filled polysilicon gate is formed in a deep trench in a lower region of the substrate and adjacent to a MOSFET body portion of the substrate. The vertical trench-filled polysilicon gate in the deep trench is isolated by dielectric material from the body portion of the MOSFET and from a word line region that is formed in the lower region of the substrate.

Claims

1. An EEPROM device structure, comprising:

a semiconductor substrate body having a surface MOSFET with a body portion and being formed in an upper region of the substrate body;

a vertical trench-filled polysilicon floating gate that is formed in a trench in a lower region of the substrate body adjacent to a current path of said surface MOSFET body portion, said vertical trench-filled polysilicon gate being isolated by dielectric material from the body portion of said surface MOSFET, wherein one side of the vertical trench-filled polysilicon gate is adjacent to the surface MOSFET body portion of said substrate; and

a memory word line region that is formed in the lower region of the substrate body adjacent to another side of the vertical trench-filled polysilicon gate and that is isolated from the vertical trench-filled polysilicon gate by dielectric material, whereby leakage of the surface MOSFET from the current path is stored using the polysilicon floating gate.

2. The EEPROM device structure of claim 1 wherein the substrate body is formed with a P-doped material, the MOSFET having source and drain regions that are formed of diffused N+ material, and the memory word line region is formed with a P-type silicon material.

3. The EEPROM device structure of claim 1 including a buried oxide layer formed beneath the substrate.

4. The EEPROM device structure of claim 1 including respective electrical contacts that are connected for providing external contacts to the MOSFET body portion, to a MOSFET source region, to a MOSFET drain, to a MOSFET gate region, and to the memory word line region.

5. An EEPROM device structure, comprising:

a semiconductor substrate body;

a surface MOSFET body portion formed in an upper region of the substrate body, the MOSFET body portion having;

a MOSFET source region;

a MOSFET drain region;

a MOSFET channel region that is formed between the MOSFET source and drain regions; and

a MOSFET gate region that is formed over said MOSFET channel region and that is insulated from said MOSFET channel region by a gate dielectric layer;

a buried vertical trench-filled polysilicon floating gate that is formed in a trench in a lower region of the substrate body adjacent to a current path in said MOSFET body portion of said substrate body, said vertical trench-filled polysilicon gate being isolated by dielectric material from the MOSFET body portion of said substrate body, wherein one side of the vertical trench-filled polysilicon gate is adjacent to the MOSFET first body portion; and

a memory word line region that is formed in the lower region of the substrate body adjacent to another side of the vertical trench-filled polysilicon floating gate and isolated from the vertical trench-filled polysilicon floating gate by dielectric material, whereby leakage of the surface MOSFET body portion in the current path is stored using the polysilicon floating gate.

6. The EEPROM device structure of claim 5 wherein the source and drain regions of the MOSFET body portion are diffused N+ material, and the memory word line region is a P-type silicon material.

7. The EEPROM device structure of claim 5 including a buried oxide layer formed beneath the substrate.

8. The EEPROM device structure of claim 5 including respective electrical contacts that are connected to the MOSFET body portion, to the MOSFET source region, to the MOSFET drain, to the MOSFET gate region, and to the word line region.

9. A dual EEPROM device structure, comprising:

a semiconductor substrate body;

a first and a second surface MOSFET body portion that are formed in an upper region of the substrate body;

each MOSFET body portion of said substrate body having;

a MOSFET source region that is formed in the MOSFET body portion of said substrate body;

a MOSFET drain region that is formed in the MOSFET body portion of said substrate body;

a MOSFET channel region that is formed between the MOSFET source and drain regions in the MOSFET body portion of said substrate body; and

a MOSFET gate region that is formed over said MOSFET channel region and that is insulated from said MOSFET channel region by a gate dielectric layer;

a first and a second vertical trench-filled polysilicon floating gate that are each formed in a respective trench in a lower region of the substrate body, wherein each trench is adjacent to a current path in a respective MOSFET body portion of the substrate body, each of said vertical trench-filled polysilicon gates being isolated by dielectric material from a respective MOSFET body portion, wherein one side of each of the vertical trench-filled polysilicon floating gate is adjacent to a respective MOSFET body portion; and

a commonly shared memory word line region that is formed in the lower region of the substrate adjacent to another side of each of the vertical trench-filled polysilicon floating gates and that is isolated from the vertical trench-filled polysilicon floating gates by dielectric material, whereby leakage of each surface MOSFET in the current path is stored using a polysilicon floating gate.

10. A method of fabricating an EEPROM device, comprising the steps of:

forming a trench in a lower region of a semiconductor substrate body;

lining said trench with a dielectric material;

filling the lined trench with polysilicon material to form a vertical trench-filled polysilicon floating gate;

forming a surface MOSFET in an upper region in a body portion of the substrate situated along and insulated from the floating gate in an orientation whereby leakage current of the surface MOSFET in a current path can be stored using the polysilicon floating gate; and

forming a word line region in the lower region of the substrate body adjacent to another side of the vertical trench-filled polysilicon floating gate and isolated from the vertical trench-filled polysilicon gate by dielectric material lining the trench.

11. The method of claim 10 including the steps of doping the surface MOSFET body portion to form a P-doped body portion, diffusing N material into the MOSFET source and drain regions, and doping the memory word line region to provide a P-type silicon material.

12. The method of claim 10 including forming a buried oxide layer formed beneath the substrate.

13. The method of claim 10 including forming respective electrical contacts that are connected to the MOSFET body portion, to the MOSFET source region, to the MOSFET drain, to the MOSFET gate region, and to the word line region.

14. An EEPROM device structure, comprising:

a semiconductor substrate body having a surface MOSFET of a first conductivity type in a first body portion and being formed in an upper region of the substrate body;

a vertical trench-filled polysilicon floating gate that is formed in a trench in a lower region of the substrate body and that has a first trench region adjacent to said surface MOSFET first body portion, said vertical trench-filled polysilicon gate being isolated by dielectric material from the first body portion of said surface MOSFET, wherein one side of said first region of the vertical trench-filled polysilicon gate is adjacent to a current path of the surface MOSFET first body portion of said substrate such that leakage of the surface MOSFET from the current path is stored in the polysilicon floating gate;

a memory word line region that is formed in the lower region of the substrate body adjacent to another side of the vertical trench-filled polysilicon gate and that is isolated from the first and second trench regions of the vertical trench-filled polysilicon gate by dielectric material; and

a second body portion of the substrate body adjacent to the first body portion having a second conductivity type, the second body portion adjacent to a second region of the vertical trench-filled polysilicon gate, whereby the first and second body portions of the substrate body together with the word line region control charge storage in the trench-filled polysilicon gate.

15. The EEPROM device structure of claim 14 wherein the second body portion of second conductivity type is formed with a P-doped material, while the MOSFET source and drain regions of first conductivity type are formed of diffused N+ material, and the memory word line region is formed with a P-type silicon material.