Patterning methods

• US 20080108224A1
• Filed: 10/12/2006
• Published: 05/08/2008
• Est. Priority Date: 10/12/2006
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Yu, Zhaoning
• Application Number:
  US11/546,663
• Publication Number:
  US 20080108224A1
• Time in Patent Office: Days
• US Class Current: 438/745
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A patterning method includes providing a substrate having an insulator layer established thereon. A silicon layer is established on the insulator layer. A mask is established on at least a portion of the silicon layer. Portions of the silicon layer and the insulator layer are removed to expose portions of the substrate, whereby the silicon layer and insulator layer covered by the mask remain on the substrate. The insulator layer is wet-etched at exposed areas, whereby a height of the insulator layer remains substantially unchanged. The mask and remaining silicon layer are removed.

Claims

1. A patterning method, comprising:

providing a substrate having an insulator layer established thereon, and a silicon layer established on the insulator layer;

establishing a mask on at least a portion of the silicon layer;

removing portions of the silicon layer and the insulator layer to expose portions of the substrate, whereby the silicon layer and insulator layer covered by the mask remain on the substrate;

wet-etching the insulator layer at exposed areas, whereby a height of the insulator layer remains substantially unchanged; and

removing the mask and the remaining silicon layer.

2. The patterning method as defined in claim 1 wherein the substrate is a silicon-on-insulator substrate including:

a silicon wafer;

the insulator layer established on the silicon wafer; and

the silicon layer established on the insulator layer.

3. The patterning method as defined in claim 2 wherein the insulator layer is silicon dioxide.

4. The patterning method as defined in claim 2 wherein prior to removing the mask and the remaining silicon layer, the method further comprises establishing a protective layer on the exposed portions of the substrate, and wherein subsequent to removing the mask and the remaining silicon layer, the method further comprises removing the protective layer.

5. The patterning method as defined in claim 4 wherein the protective layer is selected from nitride, metals, polymers, resist materials, and combinations thereof.

6. The patterning method as defined in claim 4 wherein establishing the protective layer is accomplished by evaporation, sputtering, spin-coating, etch-back or combinations thereof, and wherein removing the protective layer is accomplished by wet-chemical etching, plasma-enhanced dry-etching or combinations thereof.

7. The patterning method as defined in claim 1 wherein wet-etching is accomplished via HF wet-etching.

8. The patterning method as defined in claim 1 wherein wet-etching decreases a width of the insulator layer.

9. The patterning method as defined in claim 8 wherein wet-etching is accomplished for a predetermined time, thereby enabling control of the width of the insulator layer.

10. The patterning method as defined in claim 8 wherein an initial width of the insulator layer is about 100 nm, and wherein the decreased width of the insulator layer is about 10 nm.

11. The patterning method as defined in claim 1 wherein establishing the mask is accomplished via lithography, lift-off processes, printing, a beam of radiation, a scanning probe, or combinations thereof.

12. The patterning method as defined in claim 11 wherein the mask is selected from metals, polymers, resist materials, and combinations thereof.

13. The patterning method as defined in claim 1 wherein removing the portions of the silicon layer and the insulator layer is accomplished by reactive ion etching.

14. The patterning method as defined in claim 1 wherein the substrate is selected from silicon, GaAs, quartz, fused silica, GaN, sapphire, and combinations thereof.

15. The patterning method as defined in claim 1 wherein removing portions of the silicon layer and the insulator layer transfers a pattern formed by the mask to the silicon layer and the insulator layer.

16. A structure, comprising:

a substrate; and

at least one insulating structure established on the substrate, the insulating structure having had a silicon layer established thereon during an HF wet-etching process and subsequently removed, the silicon layer enabling a height of the insulating structure to remain substantially unchanged during the HF wet-etching process.

17. The structure as defined in claim 16 wherein the substrate is a silicon wafer, wherein the insulating structure is formed of silicon dioxide, and wherein the structure further comprises a protective layer established on the substrate during the HF wet-etching process.

18. A patterning method, comprising:

establishing an insulator layer on a substrate, the insulator layer having a predetermined height;

establishing a silicon layer on the insulator layer;

establishing a mask on at least a portion of the silicon layer, thereby forming a pattern;

removing portions of the silicon layer and the insulator layer not covered by the mask, thereby exposing portions of the substrate and transferring the pattern to the silicon layer and the insulator layer;

HF wet-etching the insulator layer at exposed areas, whereby the predetermined height of the insulator layer remains substantially unchanged, and a width of the insulator layer decreases;

removing the mask; and

removing the remaining silicon layer, thereby exposing the etched insulator layer.

19. The patterning method as defined in claim 18 wherein the substrate is silicon, wherein prior to removing the remaining silicon layer, the method further comprises establishing a protective layer on the exposed portions of the substrate, and wherein subsequent to removing the remaining silicon layer, the method further comprises removing the protective layer.

20. The patterning method as defined in claim 18 wherein HF wet-etching is accomplished for a predetermined time, thereby enabling control of the width of the insulator layer.