Protocol independent bridge
First Claim
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1. A bridge comprising:
- a first universal asynchronous receiver/transmitter (UART) for coupling to a serial bus that receives data packets;
a protocol independent module that has a timer set to a desired time to detect a start and end of a data packet received from the serial bus; and
a wireless transceiver coupled to the universal asynchronous receiver/transmitter.
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Abstract
A wireless bridge includes a first universal asynchronous receiver/transmitter (UART) for coupling to a serial bus that receives data packets. A protocol independent module has a timer set to a desired time to detect a start and/or an end of a data packet received from the serial bus. A wireless transceiver is coupled to the universal asynchronous receiver/transmitter for sending and receiving data packets.
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Citations
20 Claims
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1. A bridge comprising:
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a first universal asynchronous receiver/transmitter (UART) for coupling to a serial bus that receives data packets; a protocol independent module that has a timer set to a desired time to detect a start and end of a data packet received from the serial bus; and a wireless transceiver coupled to the universal asynchronous receiver/transmitter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
coupling a wireless bridge circuit to a hardwire serial bus connection of each of a device and a controller, wherein the wireless bridge circuit performs a method comprising; receiving serial information from a serial hard wired bus; transmitting serial information to a serial hard wired bus; setting a timer when a stream of serial data is received; and indicating a packet has been received after a predetermined time. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A wireless bridge circuit for coupling to devices via a hard wired serial bus, the wireless bridge circuit comprising:
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means for receiving serial information from a serial hard wired bus; means for transmitting serial information to a serial hard wired bus; means for setting a timer when a serial bit is received; and means for indicating a packet has been received after a predetermined time. - View Dependent Claims (18, 19, 20)
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Specification