METHOD AND APPARATUS FOR VERIFYING FAULT TOLERANT CONFIGURATION

• US 20080109584A1
• Filed: 11/06/2006
• Published: 05/08/2008
• Est. Priority Date: 11/06/2006
• Status: Active Grant

• Current Assignee: Dot Hill Systems Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Dot Hill Systems Corporation (Seagate Technology Holdings Plc)
• Inventors: Kalwitz, George Alexander
• Granted Patent: US 7,793,145 B2
• Time in Patent Office: Days
• US Class Current: 710/104
• CPC Class Codes: G06F 11/1616 where the redundant component is an I/O device or an adapter therefor
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality

Abstract

The verification of fault-tolerant connections between redundant controller pairs and nodes is provided. In particular, a node identifier seen at one port of the controllers is compared to the node identifier seen at another port of the controllers. In response to determining that proper connections have not been made, an error or warning signal may be generated. In addition, where supported by dynamic port configuration, the ports of the controllers may be reconfigured in response to the comparison to effect proper connections. In response to determining that proper connections have been made, a signal verifying that proper connections have been made may be generated.

Claims

1. A method for verifying cabling in a computer system, comprising:

determining an identifier associated with a node connected to a first port of a first controller;

determining an identifier associated with a node connected to a first port of a second controller;

comparing said determined identifiers to determine whether the identifier associated with the node connected to the first port of said first controller is the same as the identifier associated with the node connected to the first port of said second controller; and

in response to said comparing, providing a signal indicating whether the connections to the first and second controllers have been properly completed.

2. The method of claim 1, wherein the same node identifier is seen at the first ports of the first and second controllers, indicating that a first node is connected to the first ports of the first and second controllers,

wherein the first port of the first controller is connected to a second port of the second controller by port interconnect circuitry,

wherein the first port of the second controller is connected to the second port of the first controller,

wherein the first node comprises a host and the first host is not connected to the first and second controllers by a switched fabric, and

wherein the provided signal indicates that the first host seen at the first ports of the first controller and the second controllers is properly connected to the first and second controllers.

3. The method of claim 2, further comprising:

determining that a switched fabric is not detected by a port of the first or second controllers.

4. The method of claim 2, further comprising:

determining that the first port of the first controller is connected to a second port of the second controller by port interconnect circuitry; and

determining that the first port of the second controller is connected to the second port of the first controller by port interconnect circuitry.

5. The method of claim 1, wherein the same node identifier is seen at the first ports of the first and second controllers, indicating that a first node is connected to the first ports of the first and second controllers,

wherein no port of the first controller is connected to any port of the second controller by port interconnect circuitry,

wherein the first node comprises a switch,

wherein the provided signal indicates that the first switch is not properly connected.

6. The method of claim 5, further comprising:

in response to said signal indicating the first node is not properly connected, configuring the first port of the first controller and the first port of the second controller as a failover pair.

7. The method of claim 1, wherein different node identifiers are seen at the first ports of the first and second controllers, indicating that a first node is connected to the first port of the first controller and that a second node is connected to the first port of the second computer system controller,

wherein no port of the first controller is connected to any port of the second controller by port interconnect circuitry,

wherein the first node comprises a first switch,

wherein the second node comprises a second switch,

the method further comprising:

determining an identifier associated with a node connected to a second port of the first controller;

determining an identifier associated with a node connected to a second port of the second controller;

wherein the identifier associated with the first node is seen at the second port of the second controller,

wherein the identifier associated with the second node is seen at the second port of the first controller, and

wherein the provided signal indicates that the first and second nodes are properly connected.

8. The method of claim 1, wherein said identifier is a world wide name, an Internet protocol address, or an iSCSI name.

9. The method of claim 1, wherein said first port of said first controller and said first port of said second controller are connected to one another by port interconnect circuitry, and wherein said identifier determined for said node connected to the first port of the first controller is not the same as the identifier determined for the node connected to the first port of the second controller, the method further comprising:

determining that at least one of the nodes uses a pair of host bus adapters for connection to a controller;

querying a user for the identifiers of the first and second nodes;

comparing the identifier entered by the user for each of the nodes to the detected identifiers;

at least one of;

a) in response to determining that the identifiers entered by the user do not match the corresponding detected identifiers, providing a signal indicating that a connection is improper;

b) in response to determining that the identifiers entered by the user match the corresponding detected identifiers, providing a signal indicating that a connection is proper.

10. The method of claim 1, further comprising:

determining an identifier associated with a node connected to a second port of the first controller; and

determining an identifier associated with a node connected to a second port of the second controller.

11. A data storage system, comprising:

a first controller, including;

a first port;

a second port;

a processor, wherein instructions executed by at least the processor of the first controller are operable to determine an identifier associated with a node connected to the first port and an identifier associated with a node connected to the second port;

a communication interface;

a second controller, including;

a first port;

a second port;

a processor, wherein instructions executed by at least the processor of the second controller are operable to determine an identifier associated with a node connected to the first port and an identifier associated with a node connected to the second port;

a communication interface;

an inter-controller communication link, where the communication interface of the first controller is in communication with the communication interface of the second controller,

wherein instructions executed by at least one of the processor of the first controller and the processor of the second controller compare the determined identifiers and provides a signal indicating whether the connections between the ports and one or more nodes have been properly completed.

12. The data storage system of claim 11, further comprising:

port interconnect circuitry, wherein the first port of the first controller is connected to the second port of the second controller, and wherein the second port of the first controller is connected to the first port of the second controller;

a first node comprising a first host, the first host including;

a host bus adapter having a first port and a second port, wherein the host bus adapter is associated with a first identifier, and wherein the identifier associated with the first host is the first identifier;

a first interconnect cable connecting the first port of the host bus adapter of the first host to the first port of the first controller;

a second interconnect cable connecting the second port of the host bus adapter of the first host to the first port of the second controller, wherein the instructions executed by the at least one of the processors provides a signal indicating that the connections between the controller ports and the first host have been properly completed.

13. The data storage system of claim 12, further comprising:

a second node comprising a second host, the second host including;

a host bus adapter having a first port and a second port, wherein the host bus adapter is associated with a second identifier, and wherein the identifier associated with the second host is the second identifier;

a third interconnect cable connecting the first port of the host bus adapter of the second host to the second port of the first controller;

a fourth interconnect cable connecting the second port of the host bus adapter of the second host to the second port of the second controller.

14. The data storage system of claim 11, further comprising:

a first node comprising a switch, wherein the first switch is associated with a first identifier;

a first interconnect cable connecting a first port of the first switch to the first port of the first controller;

a second interconnect cable connecting a second port of the first switch to the second port of the second controller;

wherein in response to determining that the same switch identifier is seen at the first port of the first controller and the second port of the second controller, one of the processors is operable to generate a signal indicating that the connections between the first switch and the first and second controllers have been properly made.

15. The system of claim 11, further comprising:

port interconnect circuitry, wherein the first port of the first controller is connected to the second port of the second controller, and wherein the second port of the first controller is connected to the first port of the second controller;

a first node comprising a first host, the first host including;

a host bus adapter having a first port and a second port, wherein the identifier for the first host is an identifier associated with the host bus adapter;

wherein in response to determining that the identifier of the host bus adapter is the identifier associated with a node connected to the first port of the first controller and the first port of the second controller one of the processors is operable to generate a signal indicating that the connections between the first host and the first and second controllers has not been properly made.

16. The system of claim 11, further comprising:

port interconnect circuitry, wherein the first port of the first controller is connected to the second port of the second controller, and wherein the second port of the first controller is connected to the first port of the second controller;

a first node comprising a first host, the first host including;

a host bus adapter having a first port and a second port, wherein the identifier for the first host is an identifier associated with the host bus adapter;

a second node comprising a second host, including;

a first port;

a second port.

17. A computer system having paired controllers, comprising:

first means for controlling, including;

first port means;

second port means;

means for determining an identity of a node connected to each of said port means;

second means for controlling, including;

first port means;

second port means;

means for determining an identity of a node connected to each of said port means and means for comparing a plurality of determined node identities;

a data link interconnecting said first means for controlling and said second means for controlling, wherein information regarding an identity of a node connected to a port means can be passed from one of said means for controlling to the other of said means for controlling;

means for providing a signal indicating whether said port means are properly connected to a node.

18. The system of claim 17, further comprising:

means for detecting a switched fabric.

19. The system of claim 18, further comprising:

means for cross-connecting said first port means of said first means for controlling to said second port means of said second means for controlling and for connecting said first port means of said second means for controlling to said second port means of said first means for controlling;

means for detecting whether said means for cross-connecting is enabled; and

means for providing an error signal to a user in response to detecting a switched fabric and that said means for cross-connecting is enabled.

20. The system of claim 17, further comprising:

means for cross-connecting said first port means of said first means for controlling to said second port means of said second means for controlling and for connecting said first port means of said second means for controlling to said second port means of said first means for controlling;

a first node, wherein a first port of said first node is coupled to said first port means of said first means for controlling by a first cable, and wherein said first node is coupled to said second port means of said second controller,

wherein said means for providing a signal indicating whether said port means are properly connected to a node provides a signal indicating that said port means are properly connected to the first node.