SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS

• US 20080109595A1
• Filed: 10/30/2007
• Published: 05/08/2008
• Est. Priority Date: 02/09/2006
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Wang, David, Schakel, Keith, Rajan, Suresh, Weber, Frederick, Sebastian Smith, Michael
• Application Number:
  US11/929,261
• Publication Number:
  US 20080109595A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit capable of communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

2. The sub-system as set forth in claim 1, wherein the command scheduling constraints include inter-device command scheduling constraints.

3. The sub-system as set forth in claim 2, wherein the inter-device command scheduling constraints are selected from the group consisting of a rank-to-rank data bus turnaround time, and an on-die-termination (ODT) control switching time.

4. The sub-system as set forth in claim 1, wherein the command scheduling constraints include intra-device command scheduling constraints.

5. The sub-system as set forth in claim 4, wherein the intra-device command scheduling constraints are selected from the group consisting of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), and a write-to-read turn-around time (tWTR).

6. The sub-system as set forth in claim 1, wherein the command scheduling constraints of the memory circuits are reduced by controlling a manner in which commands are issued to the memory circuits.

7. The sub-system as set forth in claim 1, wherein the memory circuits include physical memory circuits, and the interface circuit is operable to simulate at least one virtual memory circuit.

8. The sub-system as set forth in claim 7, wherein the at least one virtual memory circuit has less command scheduling constraints than the physical memory circuits.

9. The sub-system as set forth in claim 7, wherein the command scheduling constraints of the physical memory circuits are reduced by issuing commands directed to a single virtual memory circuit, to a plurality of different physical memory circuits.

10. The sub-system as set forth in claim 6, wherein the commands are selected from the group consisting of row-access commands and column-access commands.

11. The sub-system as set forth in claim 6, wherein the commands are issued to different memory circuits utilizing separate busses.

12. The sub-system as set forth in claim 1, wherein the reduction of the command scheduling constraints of the memory circuits results in an increase of in a command issue rate.

13. The sub-system as set forth in claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

14. The sub-system as set forth in claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advancedd memory buffer (AMB).

15. The sub-system as set forth in claim 1, wherein the interface circuit and the memory circuits take the form of a stack.

16. The sub-system as set forth in claim 1, wherein the memory circuits include a plurality of dynamic random access memory (DRAM) circuits.

17. A method, comprising:

interfacing a plurality of memory circuits and a system; and

reducing command scheduling constraints of the memory circuits.

18. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the memory circuits, the interface circuit operable to interface the memory circuits for reducing command scheduling constraints of the memory circuits.

19. The system as set forth in claim 18, wherein the memory circuits and the interface circuit are positioned on a dual in-line memory module (DIMM).

20. the system as set forth in claim 18, wherein the memory circuits and the interface circuit are positioned on a memory module that remains in communication with a processor via a bus.