Method and apparatus for refresh management of memory modules

• US 20080109598A1
• Filed: 10/30/2007
• Published: 05/08/2008
• Est. Priority Date: 07/31/2006
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Wang, David, Smith, Michael John, Rajan, Suresh Natarajan, Schakel, Keith
• Application Number:
  US11/929,655
• Publication Number:
  US 20080109598A1
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, dock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller. and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

Claims

1. An interface circuit configured to manage refresh command sequences, the interface circuit comprising:

a system interface adapted to receive a refresh command from a memory controller;

a means for determining the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller; and

at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.

2. The interface circuit of claim 1, further comprising:

a measurement unit configured to perform analog signal measurements and to determine a configuration of the two or more memory devices; and

a calculation unit configured to determine the timing for issuing staggered refresh commands to the two or more memory devices based on measurements received from the measurement unit and the refresh command received from the memory controller.

3. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine analog pin characteristics of the two or more memory devices.

4. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine timing responses at selected logic threshold levels.

5. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine a timing response at a peak detected voltage change, a duration and a response ring.

6. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of measurements to determine an operating of each of the two or more memory devices.

7. The interface circuit of claim 1, further comprising a means for computing two staggered refresh cycles for the two memory devices that are staggered by an amount of time equal to approximately half a single refresh cycle associated with the refresh command received from the memory controller.

8. The interface circuit of claim 1, further comprising a means for computing four staggered refresh cycles for eight memory devices coupled to the interface circuit that are staggered by an amount of time equal to approximately a quarter of a single refresh cycle associated with the refresh command received from the memory controller.

9. The interface circuit of claim 1, further comprising a means for computing eight staggered refresh cycles for sixteen memory devices coupled to the interface circuit that are staggered by an amount of time equal to approximately an eighth of a single refresh cycle associated with the refresh command received from the memory controller.

10. The interface circuit of claim 1, further comprising a means for determining optimized timing for staggered refresh operations that minimize instantaneous power supply load.

11. The interface circuit of claim 1, wherein the system interface further comprises a memory address signal interface, a memory control signal interface, a memory clock signal interface, and a memory data signal interface.

12. The interface circuit of claim 1, further comprising emulation logic capable of emulating an interface protocol of each of the two or more memory devices.

13. The interface circuit of claim 1, further comprising a scheduler configured to order the staggered refresh commands being generated for the two or more memory devices.

14. The interface circuit of claim 1, wherein the two or more memory devices are arranged in one or more stacks, and each staggered refresh cycle is transmitted to two memory devices residing within the same stack.

15. The interface circuit of claim 14, wherein each of the two or more memory devices comprises a dynamic random access memory chip.

16. The interface circuit of claim 14, wherein the two or more memory devices are arranged in one stack, and the interface circuit is integrated within the one stack.

17. The interface circuit of claim 16, wherein the interface circuit comprises an intelligent buffer chip.

18. The interface circuit of claim 17, wherein the two or more memory devices comprise dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line memory module.

19. The interface circuit of claim 1, wherein the interface circuit is coupled directly to a memory module.

20. The interface circuit of claim 19, wherein the memory module comprises a dual in-line memory module.