ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY

• US 20080109629A1
• Filed: 11/05/2007
• Published: 05/08/2008
• Est. Priority Date: 11/04/2006
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Karamcheti, Vijay, Parekh, Rajesh, Singhai, Ashish, Okin, Kenneth A., Ganapathy, Kumar
• Granted Patent: US 7,774,556 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/5016 : the resource being the memory
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Claims

1. A method of managing a main memory that includes symmetric memory components associated with a first collection of memory operations and asymmetric memory components associated with a second collection of memory operations, where the symmetric memory components are each configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component, and where the asymmetric memory components are each configured to enable block write operations in which an address within a block of one of the asymmetric memory components affects the availability of other addresses within the block of the asymmetric memory component, the method comprising:

receiving, on a central processing unit (CPU), a command from an application to read data associated with a virtual address that is mapped to the main memory;

determining, using the memory management unit, that the virtual address is mapped to one of the symmetric memory components of the main memory;

accessing memory use characteristics indicating how the data associated with the virtual address has been accessed;

determining, based on the memory use characteristics, that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory;

loading, using the CPU, the data associated with the virtual address to the asymmetric memory component of the main memory;

receiving, after the loading and using the memory management unit, a command from the application to read the data associated with the virtual address; and

retrieving, responsive to the received command, the data associated with the virtual address from the asymmetric memory component of the main memory.

2. The method of claim 1 wherein the symmetric memory component includes dynamic random access memory (DRAM) and the asymmetric memory component includes NOR flash, where the DRAM is configured to enable random access write operations in which an address within a block of the DRAM is written without affecting the availability of other addresses within the block of the DRAM, and where the NOR flash is configured to enable block write operations in which an address within a block of one of the NOR flash affects the availability of other addresses within the block of the NOR flash, and further comprising:

determining, using the memory management unit, that the virtual address is mapped to one of the DRAM blocks;

accessing memory use characteristics indicating how the data associated with the virtual address has been accessed within the DRAM block;

determining, based on the memory use characteristics, that the data associated with the virtual address has access characteristics suited to NOR flash of the main memory;

loading, using the CPU, the data associated with the virtual address to the NOR flash of the main memory;

receiving, after the loading and using the memory management unit, a command from the application to read the data associated with the virtual address; and

retrieving, responsive to the received command, the data associated with the virtual address from the NOR flash of the main memory.

3. The method of claim 1 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component of the main memory includes determining that the access characteristics are related to a profile that indicates whether the data should be loaded to the asymmetric memory component based on a number of times the data has been read and the number of times that the data has been updated using a write instruction.

4. The method of claim 1 wherein:

the asymmetric memory component has asymmetric access characteristics including;

(1) the asymmetric memory component performs read operations at a first rate and performs write operations at a second rate that is more than an order of magnitude different than the first rate,

(2) the asymmetric memory component uses an asymmetric memory access protocol, and

(3) the asymmetric memory component includes non-volatile storage capability; and

the symmetric memory component has symmetric access characteristics including;

(1) the symmetric memory component performs read operations at a rate that that differs by less than an order of magnitude from a rate at which write operations are performed,

(2) the symmetric memory component uses a symmetric memory access protocol, and

(3) the symmetric memory component includes a volatile storage capability.

5. The method of claim 1 wherein loading the data associated with the virtual address to the asymmetric memory component of main memory includes loading the data as part of a block write that includes additional content that is different than the data.

6. The method of claim 1 further comprising:

identifying, from a first read instruction, the data to be loaded to the asymmetric memory component as a first portion;

storing the first portion in the symmetric memory component of the main memory;

identifying, from a second read instruction, other content to be loaded to the symmetric memory component as a second portion;

storing the second portion in the symmetric memory component of the main memory;

structuring the first portion and the second portion as a block to be written to the asymmetric memory component; and

writing the block that includes the first portion and the second portion to the asymmetric memory component.

7. The method of claim 1 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component includes:

determining that an application is operating in a constrained environment for memory resources; and

adjusting constrained metrics used in determining whether to load the data to the asymmetric memory component to increase a likelihood that the data is loaded the asymmetric memory component.

8. The method of claim 1 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component includes:

determining that an application is unconstrained for memory resources; and

using unconstrained metrics to determine whether to load the data to the asymmetric memory component.

9. The method of claim 1 further comprising setting a write protection bit for the data that has been loaded to asymmetric memory that regulates subsequent write access to the virtual address for the data.

10. The method of claim 1 wherein determining, based on the memory use characteristics, that the data associated with the virtual address has the access characteristics suited to the asymmetric memory component of the main memory includes determining that a first threshold number of reads of the data has occurred in an observation window.

11. The method of claim 1 further comprising determining that the data associated with the virtual address does not have the access characteristics suited to the asymmetric memory component of the main memory in response to determining that a second threshold number of updates to the data has been requested in an observation window.

12. A system that manages a main memory that includes symmetric memory components associated with a first collection of memory operations and asymmetric memory components associated with a second collection of memory operations, where the symmetric memory components are each configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component, and where the asymmetric memory components are each configured to enable block write operations in which an address within a block of one of the asymmetric memory components affects the availability of other addresses within the block of the asymmetric memory component, the system instructions that when executed on a processor perform operations that include:

receiving, on a central processing unit (CPU), a command from an application to read data associated with a virtual address that is mapped to the main memory;

determining, using the memory management unit, that the virtual address is mapped to one of the symmetric memory components of the main memory;

accessing memory use characteristics indicating how the data associated with the virtual address has been accessed;

determining, based on the memory use characteristics, that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory;

loading, using the CPU, the data associated with the virtual address to the asymmetric memory component of the main memory;

receiving, after the loading and using the memory management unit, a command from the application to read the data associated with the virtual address; and

retrieving, responsive to the received command, the data associated with the virtual address from the asymmetric memory component of the main memory.

13. The system of claim 12 wherein the symmetric memory component includes dynamic random access memory (DRAM) and the asymmetric memory component includes NOR flash, where the DRAM is configured to enable random access write operations in which an address within a block of the DRAM is written without affecting the availability of other addresses within the block of the DRAM, and where the NOR flash is configured to enable block write operations in which an address within a block of one of the NOR flash affects the availability of other addresses within the block of the NOR flash, and further comprising:

determining, using the memory management unit, that the virtual address is mapped to one of the DRAM blocks;

accessing memory use characteristics indicating how the data associated with the virtual address has been accessed within the DRAM block;

determining, based on the memory use characteristics, that the data associated with the virtual address has access characteristics suited to NOR flash of the main memory;

loading, using the CPU, the data associated with the virtual address to the NOR flash of the main memory;

receiving, after the loading and using the memory management unit, a command from the application to read the data associated with the virtual address; and

retrieving, responsive to the received command, the data associated with the virtual address from the NOR flash of the main memory.

14. The system of claim 12 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component of the main memory includes determining that the access characteristics are related to a profile that indicates whether the data should be loaded to the asymmetric memory component based on a number of times the data has been read and the number of times that the data has been updated using a write instruction.

15. The system of claim 12 wherein:

the asymmetric memory component has asymmetric access characteristics including;

(1) the asymmetric memory component performs read operations at a first rate and performs write operations at a second rate that is more than an order of magnitude different than the first rate,

(2) the asymmetric memory component uses an asymmetric memory access protocol, and

(3) the asymmetric memory component includes non-volatile storage capability; and

the symmetric memory component has symmetric access characteristics including;

(1) the symmetric memory component performs read operations at a rate that that differs by less than an order of magnitude from a rate at which write operations are performed,

(2) the symmetric memory component uses a symmetric memory access protocol, and

(3) the symmetric memory component includes a volatile storage capability.

16. The system of claim 12 wherein loading the data associated with the virtual address to the asymmetric memory component of main memory includes loading the data as part of a block write that includes additional content that is different than the data.

17. The system of claim 12 further comprising:

identifying, from a first read instruction, the data to be loaded to the asymmetric memory component as a first portion;

storing the first portion in the symmetric memory component of the main memory;

identifying, from a second read instruction, other content to be loaded to the symmetric memory component as a second portion;

storing the second portion in the symmetric memory component of the main memory;

structuring the first portion and the second portion as a block to be written to the asymmetric memory component; and

writing the block that includes the first portion and the second portion to the asymmetric memory component.

18. The system of claim 12 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component includes:

determining that an application is operating in a constrained environment for memory resources; and

adjusting constrained metrics used in determining whether to load the data to the asymmetric memory component to increase a likelihood that the data is loaded the asymmetric memory component.

19. The system of claim 12 wherein determining that the data associated with the virtual address has access characteristics suited for use in the asymmetric memory component includes:

determining that an application is unconstrained for memory resources; and

using unconstrained metrics to determine whether to load the data to the asymmetric memory component.

20. The system of claim 12 further comprising setting a write protection bit for the data that has been loaded to asymmetric memory that regulates subsequent write access to the virtual address for the data.

21. The system of claim 12 wherein determining, based on the memory use characteristics, that the data associated with the virtual address has the access characteristics suited to the asymmetric memory component of the main memory includes determining that a first threshold number of reads of the data has occurred in an observation window.

22. The system of claim 12 further comprising determining that the data associated with the virtual address does not have the access characteristics suited to the asymmetric memory component of the main memory in response to determining that a second threshold number of updates to the data has been requested in an observation window.

23. A system that manages a main memory that includes symmetric memory components associated with a first collection of memory operations and asymmetric memory components associated with a second collection of memory operations, where the symmetric memory components are each configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component, and where the asymmetric memory components are each configured to enable block write operations in which an address within a block of one of the asymmetric memory components affects the availability of other addresses within the block of the asymmetric memory component, the system instructions that when executed on a processor perform operations that include:

means for receiving, on a central processing unit (CPU), a command from an application to read data associated with a virtual address that is mapped to the main memory;

means for determining, using the memory management unit, that the virtual address is mapped to one of the symmetric memory components of the main memory;

means for accessing memory use characteristics indicating how the data associated with the virtual address has been accessed;

means for determining, based on the memory use characteristics, that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory;

means for loading, using the CPU, the data associated with the virtual address to the asymmetric memory component of the main memory;

means for receiving, after the loading and using the memory management unit, a command from the application to read the data associated with the virtual address; and

means for retrieving, responsive to the received command, the data associated with the virtual address from the asymmetric memory component of the main memory.