FORWARD ERROR CORRECTION ENCODING FOR MULTIPLE LINK TRANSMISSION CAPATIBLE WITH 64B/66B SCRAMBLING

• US 20080109707A1
• Filed: 11/03/2006
• Published: 05/08/2008
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dell, Timothy, Glaise, Rene
• Granted Patent: US 7,996,747 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H03M 13/03 Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x¹⁰+x³+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x⁶+1.

Claims

1. A method of generating a forward error correction (FEC) code for a packet-based digital communications system, the method comprising:

applying a first encoding algorithm to a first dataword;

applying a second encoding algorithm to the first dataword;

generating a first checkbit sequence for the first dataword;

appending the checkbit sequence to the first dataword;

scrambling the first dataword at a source node;

transmitting the first dataword on a data transmission link from the source node to a destination node;

descrambling the transmitted first dataword at the destination node;

generating a second checkbit sequence based on the transmitted dataword;

comparing the first checkbit sequence with the second checkbit sequence;

determining whether the received dataword contains a first bit error; and

correcting the first bit error and a first and second replicated bit error.

2. The method according to claim 1, further comprising representing a plurality of encoded datawords in a first matrix, wherein a plurality of checkbit sequences corresponding to each of the plurality of datawords is appended to the first matrix.

3. The method according to claim 1 further comprising appending a checkbit sequence to each of a corresponding plurality of encoded datawords.

4. The method according to claim 1, further comprising concatenating a plurality of datawords and providing a single checkbit sequence for error correction.

5. The method according to claim 1, wherein the data transmission link comprises a multiple link communications channel capable of inverse multiplexing.

6. The method according to claim 1, wherein the scrambling step further comprises employing a 64B/66B scrambling protocol.

7. The method according to claim 1, wherein the first encoding algorithm comprises a multiplication operation with the first dataword and a Hamming code polynomial as primary arguments.

8. The method according to claim 7, wherein the Hamming code determines the maximum length of the packet size, including error correction and parity bits.

9. The method according to claim 7, wherein the Hamming code is generated from a tenth order irreducible polynomial of the form:

H(x)=x¹⁰+x³+1.

10. The method according to claim 1, wherein the second encoding algorithm comprises a multiplication operation with the first dataword and a bit-interleaved parity code of degree n as primary arguments.

11. The method according to claim 10, wherein the BIP code comprises a sixth order polynomial of the form:

B(x)=x⁶+1.

12. The method according to claim 1, wherein the digital communications system transmits and receives a packetized data stream in an ATM format.

13. The method according to claim 1, wherein the data transmission link comprises a single serializer-deserializer link.

14. The method according to claim 3, further comprising generating an H-matrix in systematic form for encoding the checkbit sequence and an error syndrome, wherein the use of the same H-matrix in non-systematic form enables the decoding of the error syndrome.

38. The system according to claim 10, wherein the BIP code comprises a sixth order polynomial of the form:

B(x)=x⁶+1.

15. A method of applying a forward error correction code to a digital signal for transmission on a serializer-deserializer link, the method comprising:

applying a Hamming code to the digital signal from an irreducible polynomial of the form H(x)=x¹⁰+x³+1;

applying a bit-interleaved parity code to the digital signal of degree n (BIP-n);

generating a first checkbit sequence 1 or the encoded digital signal;

appending the first checkbit sequence to the encoded digital signal;

scrambling the encoded digital signal and the first checkbit sequence using a 64B/66B scrambling protocol;

transmitting the scrambled and encoded digital signal over the serializer-deserializer link;

descrambling the transmitted digital signal at a receiver node;

generating a second checkbit sequence at the receiver node;

comparing the first checkbit sequence with the second checkbit sequence;

determining whether the transmitted digital signal contains a first bit error; and

correcting the first bit error, a first replicated error and a second replicated error.

16. The method according to claim 15, wherein the BIP code comprises a sixth order polynomial of the form:

B(x)=x⁶+1.

17. A method of building a forward error correction (FEC) code for a packet-based digital communications system using a self-synchronized scrambler, said method comprising the steps of:

determining the power (n) of a bit interleave parity (BIP-n) code capable of discriminating between all error patterns of a single transmission error and replications thereof generated by said self-synchronized scrambler upon reception of transmitted FEC encoded frames;

determining the power of a polynomial used to generate a Hamming code of a length compatible with the packet size of said packet-based digital communications system;

combining said BIP-n code and said Hamming code to form said FEC code and obtain, upon reception of said transmitted FEC encoded frames, a set of unique syndromes for all combinations of said single bit transmission errors and replications; and

allowing the FEC code to correct all single transmission errors and their replications by the self-synchronized scrambler while preserving a bit transition density of a physical layer as provided by said scrambler.

18. The method of claim 17 wherein power (n) of said BIP-n code is such that all powers of the polynomial defining said self-synchronized scrambler have a unique residue modulo n.

19. The method of claim 17 wherein the power of said Hamming polynomial is such that the FEC code length is greater than or equal to the packet size of said digital communications system.

20. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating a forward error correction (FEC) code for a packet-based digital communications system, said method steps comprising:

applying a first encoding algorithm to a first dataword;

applying a second encoding algorithm to the first dataword;

generating a first checkbit sequence for the first dataword;

appending the checkbit sequence to the first dataword;

scrambling the first dataword at a source node;

transmitting the first dataword on a data transmission link from the source node to a destination node;

descrambling the transmitted first dataword at the destination node; and

generating a second checkbit sequence based on the transmitted dataword;

comparing the first checkbit sequence with the second checkbit sequence;

determining whether the received dataword contains a first bit error; and

correcting the first bit error and correcting a first and second replicated bit error.

21. The program storage device of claim 20, wherein generating the first checkbit sequence for the first dataword comprises the logical XOR of a plurality of bits forming the first dataword.

22. The program storage device of claim 20, wherein the comparing step produces a first error syndrome representing the number of errors contained in the received dataword.

23. The program storage device of claim 20, wherein the comparing step produces a second error syndrome representing the location of a first error and a first or second replicated error spaced according to the powers of a scrambling polynomial.

24. The program storage device of claim 20, further comprising detecting a second bit error.

25. The program storage device according to claim 20, wherein the program of instructions further comprises transposing an error syndrome vector to a systematic H-matrix form.

26. The program storage device according to claim 20, wherein the first encoding algorithm comprises a multiplication operation with the packetized dataword and a Hamming code polynomial as primary arguments.

27. The program storage device according to claim 26, wherein the Hamming code determines the maximum length of the packet size, including error correction and parity bits.

28. The program storage device according to claim 26, wherein the Hamming code is generated from a tenth order irreducible polynomial of the form:

H(x)=x¹⁰+x³+1.

29. The program storage device according to claim 20, wherein the second encoding algorithm comprises a multiplication operation with the first dataword and a bit-interleaved parity code of degree n as primary arguments.

30. The program storage device according to claim 20, wherein the BIP code comprises a sixth order polynomial of the form:

B(x)=x⁶+1.

31. A system for generating a forward error correction (FEC) code for a packetized dataword, the method comprising:

a first encoder adapted to apply a first encoding algorithm to the packetized dataword;

a second encoder adapted to apply a second encoding algorithm to the packetized dataword;

a scrambler element adapted to apply a scrambling polynomial to the encoded packetized dataword at a source node;

a communications channel link adapted to transmit the encoded and scrambled packetized dataword from the source node to a destination node;

a descrambler element adapted to apply a descrambling polynomial to the transmitted packetized dataword at the destination node;

a decoder element adapted to decode the encoded packetized dataword at a destination node; and

an XOR logic element adapted to compare a regenerated checkbit sequence with a transmitted checkbit sequence appended to the transmitted packetized dataword.

32. The system according to claim 31, wherein the scrambling element employs a 64B/66B scrambling protocol.

33. The system according to claim 31, wherein the descrambling function comprises an inverse mathematical operation of the scrambling polynomial.

34. The system according to claim 31, wherein the first encoding algorithm comprises a multiplication operation with the packetized dataword and a Hamming code polynomial as primary arguments.

35. The system according to claim 34, wherein the Hamming code determines the maximum length of the packet size, including error correction and parity bits.

36. The system according to claim 34, wherein the Hamming code is generated from a tenth order irreducible polynomial of the form:

H(x)=x¹⁰+x³+1.

37. The system according to claim 31, wherein the second encoding algorithm comprises a multiplication operation with the first dataword and a bit-interleaved parity code of degree n as primary arguments.