High Efficiency Light-Emitting Diodes

• US 20080111123A1
• Filed: 10/08/2005
• Published: 05/15/2008
• Est. Priority Date: 10/08/2004
• Status: Abandoned Application

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Odnoblyudov, Vladimir, Tu, Charles
• Application Number:
  US11/576,992
• Publication Number:
  US 20080111123A1
• Time in Patent Office: Days
• US Class Current: 257/13
• CPC Class Codes: H01L 21/02392 Phosphides
• CPC Class Codes: H01L 21/02461 Phosphides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

High efficiency LEDs produced using a direct-bandgap AlGaInNSbAsP material system grown directly on GaP substrates.

Claims

1. An LED structure comprising the following layers:

a) n-type GaP substrate

b) Al_xGa_1-xP buffer layer n-type or undoped

c) Al_yGa_1-yP holes-leakage-preventing layer, n-type or undoped

d) a plurality of the following-layers;

Al_zGa_1-zP barrier/Al_nIn_mGa_1-m-nN_cAs_vSb_kP_1-c-v-k active layer n- or p-type or undoped, and

e) In_wAl_sGa_1-s-wP cap/contact layer p-type or undoped

2. The LED structure of claim 1 with compositions x, y, z, n, m, c, v, s, w, k such that:

0≦

x≦

y≦

1, 0≦

z, n, m, c, v, s, w, k≦

1.

4. The LED structure of claim 1, in which the Al_tGa_1-tP, n-type, p-type or undoped, current spread/blocking layer lies before, inside, or after the In_wAl_sGa_1-s-wP cap/contact layer.

6. The LED structure of claim 1, further comprising n-type or p-type delta doping layers deposited on the interfaces between layers, or any place inside the specified layers.

8. The LED structure of claim 4, further comprising n-type or p-type delta doping layers deposited on the interfaces between layers, or any place inside the specified layers.

10. The LED structures of claims 1, 3, 4, or 5 in which the layers, or parts of the layers are grown using the super lattices or “

digital alloy”

technique.

11. The LED structures of claims 1, 3, 4 or 5 in which improvement of the optical performance is achieved by applying annealing the structures, during or after the growth with an annealing temperature higher than the highest growth temperature used.

3. An LED structure comprising the following layers:

a) p-type GaP substrate

b) Al_xGa_1-xP buffer layer p-type or undoped

c) a plurality of the following layers;

Al_zGa_1-zP barrier/Al_nIn_mGa_1-m-nN_cAs_vSb_kP_1-c-v-k active layer n- or p-type or undoped

d) Al_yGa_1-yP holes leakage preventing layer n-type or undoped

e) In_wAl_sGa_1-s-wP cap/contact layer n-type or undoped.

5. The LED structure of claim 3, in which the Al_tGa_1-tP, n-type, p-type or undoped current spreading/blocking layer lies before, inside, or after the Al_xGa_1-xP buffer layer.

7. The LED structure of claim 3, further comprising n-type or p-type delta doping layers deposited on the interfaces between layers, or any place inside the specified layers.

9. The LED structure of claim 5, further comprising n-type or p-type delta doping layers deposited on the interfaces between layers, or any place inside the specified layers.