SEMICONDUCTOR DEVICE, METHOD OF MAKING THE SAME AND LIQUID CRYSTAL DISPLAY DEVICE

• US 20080111134A1
• Filed: 01/04/2008
• Published: 05/15/2008
• Est. Priority Date: 10/29/1999
• Status: Abandoned Application

• Current Assignee: Kiyokazu Nakagawa, Masanobu Miyao, Nobuyuki Sugii, Seang-Kee Park, Shinya Yamaguchi
• Original Assignee: Kiyokazu Nakagawa, Masanobu Miyao, Nobuyuki Sugii, Seang-Kee Park, Shinya Yamaguchi
• Inventors: Sugii, Nobuyuki, Yamaguchi, Shinya, Miyao, Masanobu, Park, Seang-kee, Nakagawa, Kiyokazu
• Application Number:
  US11/969,488
• Publication Number:
  US 20080111134A1
• Time in Patent Office: Days
• US Class Current: 257/67
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 27/1281 by using structural features to control crystal growth, e.g. placement of grain filters
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Claims

1. A thin-film semiconductor device comprising an insulator, a semiconductor thin-film formed on said insulator and a transistor comprising a source region, a drain region, a channel region and a gate electrode formed at the surface of said semiconductor thin-film, said semiconductor thin-film having amorphous regions of Type-IV element and dendrite crystal regions of Type-IV element connecting said source region and said drain region.

2. A thin-film semiconductor device as claimed in claim 1, wherein, in at least one current path formed by said dendrite crystal region connecting said source region and said drain region, at least one of the crystal grain boundaries crossing said current path is {111} twin of Diamond structure.

3. A thin-film semiconductor device comprising an insulating substrate, a poly-crystal semiconductor thin-film formed on said insulating substrate and a transistor comprising a source region, a drain region, a channel region and a gate electrode formed at the surface of said poly-crystal semiconductor thin-film, said poly-crystal thin-film comprising crystal of an element selected from the group of Type-IV element and the alloy thereof, the crystal boundaries of said poly-crystal thin-film being {111} twin of Diamond structure, said poly-crystal thin-film having a seed metal layer of a metal M selected the group of Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ru, Rh, Pd, Ag, Os, Ir, Pt, Au and the alloy thereof, or of a compound MxAy of said metal M and said Type-IV element A (x and y are mixing crystal ratio of M and A), or of a layered structure of said metal M and said Type-IV element A provided at the surface thereof near said channel region of said transistor.

4. A method of manufacturing a thin-film semiconductor device comprising the steps of forming an amorphous semiconductor thin-film partially provided with a seed crystal metal at the surface thereof on a major surface of an insulator, and crystallizing said semiconductor thin-film with a direction from said seed crystal metal to said major surface of said insulator substrate by annealing said semiconductor thin-film.

9. A method of manufacturing a thin-film semiconductor device as claimed in claim 4, wherein said semiconductor thin-film is of the element selected from the group of Type-IV element and an alloy thereof.

10. A method of manufacturing a thin-film semiconductor device as claimed in claim 4, wherein said seed crystal metal is of the element selected from the group of Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ru, Rh, Pd, Ag, Os, Ir, Pt and Au, alloys thereof, and compounds of said metal and Type-IV element, or is of a laminated structure of said metal and said Type-IV element.

5. A method of manufacturing a thin-film semiconductor device comprising the steps of depositing amorphous Si thin-film at the upper part of an insulator, providing seed crystal metal at the surface of said thin-film except for the surface of channel forming area, forming crystal grains of said Si joined by twin-boundaries in the surface of said thin-film in said channel forming area by heat treatment of said amorphous Si thin-film, and providing a gate electrode at the surface of said channel forming area of said Si thin-film via a gate insulating film.

11. A method of manufacturing a thin-film semiconductor device as claimed in claim 5, wherein a bottle-neck region is formed between said seed crystal metal and the channel forming surface area in said amorphous thin-film before conducting said heat treatment, by selectively removing a part of said amorphous thin-film.

6. A method of manufacturing a thin-film semiconductor device comprising the steps of depositing an amorphous Si thin-film with the thickness of 10 to 150 nm at the upper part of an insulator, providing seed crystal metal on the surface of said thin-film except for the surface of a channel forming area, annealing said amorphous Si thin-film at the temperature of 600°

C. or lower, and providing a gate electrode to the surface of said channel forming area of said Si thin-film via a gate insulating film.

7. A method of manufacturing a thin-film semiconductor device as claimed in claim 6, wherein said insulator is of a glass substrate and said amorphous Si thin-film is formed by heat treatment under the temperature range from 300°

C. to 600°

C.

8. A method of manufacturing a thin-film semiconductor device comprising the steps of depositing a first amorphous Si thin-film at the upper part of an insulator, providing a seed crystal metal to a first thin-film area except for an active region of the thin-film transistor, crystallizing said first Si thin-film by annealing, depositing a second amorphous Si thin-film at the upper part of said first Si thin-film thus-obtained, forming crystal grains of Si jointed by twin boundaries in said second thin-film area of the active region by annealing said second thin-film, providing a gate insulating film on the surface of said active region of said second thin-film, and providing a gate electrode on said gate insulating film.