INTEGRATION OF A SiGe- OR SiGeC-BASED HBT WITH A SiGe- OR SiGeC-STRAPPED SEMICONDUCTOR DEVICE

• US 20080111154A1
• Filed: 11/10/2006
• Published: 05/15/2008
• Est. Priority Date: 11/10/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven
• Granted Patent: US 7,705,426 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.

Claims

1. An integrated semiconductor device comprising:

a semiconductor substrate;

a first semiconductor device comprising a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein said HBT comprises a base region containing a first portion of a SiGe or SiGeC layer; and

a second semiconductor device located in a second region of the semiconductor substrate, wherein said second semiconductor device comprises an interconnect containing a second portion of the SiGe or SiGeC layer.

2. The integrated semiconductor device of claim 1, wherein the second portion of the SiGe or SiGeC layer comprises a polycrystalline section and a single crystal section.

3. The integrated semiconductor device of claim 1, wherein said second semiconductor device comprises a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer.

4. The integrated semiconductor device of claim 1, wherein the semiconductor substrate is doped with a p-type dopant species, wherein said second semiconductor device comprises a trench-biased PNPN silicon controlled rectifier, which includes a p-type anode that is located over an n-well in the semiconductor substrate, an n-type cathode that is located over the semiconductor substrate and is spaced apart from the n-well, and a polysilicon-filled trench that is located in the semiconductor substrate abutting the n-well region, and wherein the second portion of the SiGe or SiGeC layer is located over and electrically contacts the polysilicon-filled trench for applying a bias voltage to said trench.

5. The integrated semiconductor device of claim 4, wherein the polysilicon-filled trench encircles the n-well.

6. The integrated semiconductor device of claim 4, wherein the polysilicon-filled trench is located at one side of the n-well between the n-well and the n-cathode.

7. The integrated semiconductor device of claim 4, wherein the trench-biased PNPN silicon controlled rectifier comprises five electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the n-well, a second additional electrode electrically connected with the p-doped semiconductor substrate, and a third additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

8. The integrated semiconductor device of claim 4, wherein the second portion of the SiGe or SiGeC layer extends to form further electrical contact with the p-doped semiconductor substrate, and wherein the trench-biased PNPN silicon controlled rectifier comprises four electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the n-well, and a second additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

9. The integrated semiconductor device of claim 4, wherein the second portion of the SiGe or SiGeC layer extends to further form electrical contact with the n-well, and wherein the trench-biased PNPN silicon controlled rectifier comprises four electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the p-doped semiconductor substrate, and a second additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

10. A method for forming an integrated semiconductor device comprising:

providing a semiconductor substrate;

forming a first semiconductor device comprising a heterojunction bipolar transistor (HBT) in a first region of the semiconductor substrate and a second semiconductor device in a second region of the semiconductor substrate;

forming a SiGe or SiGeC layer over the first and second regions, wherein a first portion of the SiGe or SiGeC layer forms a base region in the HBT, and wherein a second portion of the SiGe or SiGeC layer forms an interconnect in said second semiconductor device.

11. The method of claim 10, wherein the second semiconductor device comprises a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer.

12. The method of claim 10, wherein the second semiconductor device comprises a trench-biased PNPN silicon controlled rectifier, which includes a p-type anode that is located over an n-well in the semiconductor substrate, an n-type cathode that is located over the semiconductor substrate and is spaced apart from the n-well, and a polysilicon-filled trench that is located in the semiconductor substrate abutting the n-well region, and wherein the second portion of the SiGe or SiGeC layer is located over and electrically contacts the polysilicon-filled trench for applying a bias voltage to said trench.

13. A semiconductor structure comprising:

a doped semiconductor substrate having a first conductivity type;

a doped well region located in the doped semiconductor substrate, wherein said doped well region has a second, opposite conductivity type;

a first doped layer located over a first portion of the doped well region, wherein said first doped layer has the first conductivity type;

a second doped layer located over a first portion of the doped semiconductor substrate and spaced apart from the doped well region, wherein said second doped layer has the second, opposite conductivity type;

a trench located in the doped semiconductor substrate and abutting the doped well region, wherein said trench comprises a conductive or semiconductor trench fill; and

a conductive layer located over and electrically connected with the trench for applying a bias voltage to the conductive or semiconductor trench fill.

14. The semiconductor structure of claim 13, wherein the conductive or semiconductor trench fill comprises polysilicon.

15. The semiconductor structure of claim 13, wherein the conductive layer comprises SiGe or SiGeC.

16. The semiconductor structure of claim 13, wherein the first conductivity type is p-type, and wherein the second conductivity type is n-type, and wherein the semiconductor structure thereby comprises a trench-biased PNPN silicon controlled rectifier.

17. The semiconductor structure of claim 16, further comprising an anode electrically connected with the first doped layer of p-type conductivity, a cathode electrically connected with the second doped layer of n-type conductivity, a first additional electrode electrically connected with the p-doped semiconductor substrate, a second additional electrode electrically connected with the n-doped well region, and a third additional electrode electrically connected with the conductive layer.

18. The semiconductor structure of claim 16, wherein the conductive layer extends to further form electrical contact with the p-doped semiconductor substrate, and wherein said semiconductor structure further comprises an anode electrically connected with the first doped layer of p-type conductivity, a cathode electrically connected with the second doped layer of n-type conductivity, a first additional electrode electrically connected with the n-doped well region, and a second additional electrode electrically connected with the conductive layer.

19. The semiconductor structure of claim 16, wherein the conductive layer extends to further form electrical contact with the n-doped well region, and wherein said semiconductor structure further comprises an anode electrically connected with the first doped layer of p-type conductivity, a cathode electrically connected with the second doped layer of n-type conductivity, a first additional electrode electrically connected with the p-doped semiconductor substrate, and a second additional electrode electrically connected with the conductive layer.

20. The semiconductor structure of claim 13, wherein the first conductivity type is n-type, wherein the second conductivity type is p-type, and wherein the semiconductor structure comprises a trench-biased NPNP silicon controlled rectifier.

21. The semiconductor structure of claim 13, wherein a third doped layer having the second, opposite conductivity type is located over a second portion of the doped well region, and wherein a fourth doped layer having the first conductivity type is located over a second portion of the doped semiconductor substrate.

22. A reversibly programmable device comprising:

a doped semiconductor substrate having a first conductivity type;

a doped well region located in the doped semiconductor substrate, wherein said doped well region has a second, opposite conductivity type;

a first doped layer located over a first portion of the doped well region, wherein said first doped layer has the first conductivity type;

a second doped layer located over a first portion of the doped semiconductor substrate and spaced apart from the doped well region, wherein said second doped layer has the second, opposite conductivity type;

a trench located in the doped semiconductor substrate and abutting the doped well region, wherein said trench comprises a conductive or semiconductor trench fill; and

a conductive layer located over and electrically connected with the trench for applying a bias voltage to the trench fill,

wherein said reversible programmable device has an unbiased trigger voltage after a ground voltage is applied to the trench fill and at least a first biased trigger voltage that is higher than the unbiased trigger voltage after a first positive bias voltage is applied to the trench fill.

23. The reversibly programmable device of claim 22, having one or more additional biased trigger voltages, which are different from the first biased trigger voltage but higher than the unbiased trigger voltage, after additional positive bias voltages that are different from the first positive bias voltage are applied to the trench fill.

24. A memory device comprising the reversibly programmable device of claim 22, wherein said memory device is in a base state characterized by the unbiased trigger voltage.

25. A memory device comprising the reversibly programmable device of claim 22, wherein said memory device is in a first programmed state characterized by the first biased trigger voltage.

26. A memory device comprising the reversibly programmable device of claim 23, wherein said memory device is in an additional programmable state characterized by one of the additional biased trigger voltages.

27. A method for programming a reversibly programmable device, comprising:

providing a reversibly programmable device that comprises;

(1) a doped semiconductor substrate having a first conductivity type, (2) a doped well region located in the doped semiconductor substrate, wherein said doped well region has a second, opposite conductivity type, (3) a first doped layer located over a first portion of the doped well region, wherein said first doped layer has the first conductivity type, (4) a second doped layer located over a first portion of the doped semiconductor substrate and spaced apart from the doped well region, wherein said second doped layer has the second, opposite conductivity type, (5) a trench located in the doped semiconductor substrate and abutting the doped well region, wherein the trench comprises a conductive or semiconductor trench fill, and (6) a conductive layer located over and electrically connected with the trench for applying a bias voltage to the trench fill;

applying a ground voltage to the trench fill through the conductive layer, thereby setting the reversibly programmable device to a base state characterized by an unbiased trigger voltage; and

applying a first positive bias voltage to the trench fill through the conductive layer, thereby setting the reversibly programmable device to a first programmed state characterized by a first biased trigger voltage that is higher than the unbiased trigger voltage.

28. The method of claim 27, further comprising applying one or more additional positive bias voltages that are different from the first positive bias voltage to the trench fill to thereby set the reversibly programmable device to one or more additional programmed states characterized by additional bias trigger voltages that are different from the first bias trigger voltage but higher than the unbiased trigger voltage.

29. The method of claim 28, comprising repeatedly applying the ground voltage, the first positive bias voltage, or the one or more additional positive vias voltages to the trench fill to thereby set the reversibly programmable device to the base state, the first programmable state, or the one or more additional programmed states.

30. A static random access memory (SRAM) cell comprising at least two trench-biased silicon controlled rectifier (SCR) devices cross-coupled with each other to form a latch network.