PROTECTIVE STRUCTURE FOR SEMICONDUCTOR SENSORS

• US 20080111161A1
• Filed: 11/08/2007
• Published: 05/15/2008
• Est. Priority Date: 11/09/2006
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: KURTH, Eberhard, SORGE, Stephan, KUNATH, Christian
• Granted Patent: US 7,728,363 B2
• Time in Patent Office: Days
• US Class Current: 257/253
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

Claims

1. An integrated semiconductor sensor for use in a state that is in direct contact with a measuring medium, comprising:

a semiconductor substrate with a first and a second doped trace region and a gap between the first and second trace regions, and an insulating layer that separates the semiconductor substrate along the gap from the measuring medium to form an ion-sensitive field-effect transistor;

a semiconducting layer that is applied to the semiconductor substrate;

a metal layer; and

an insulating layer,

wherein the insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

2. The integrated semiconductor sensor according to claim 1, wherein the metal layer comprises a face turned away from the insulating layer, in order to be able to be brought into contact with the measuring medium via a protective layer or directly.

3. The integrated semiconductor sensor according to claim 2, wherein the protective layer comprises an oxide layer.

4. The integrated semiconductor sensor according to claim 1, wherein the metal layer and/or the protective layer is formed such that the contact with the measuring medium is of low impedance.

5. The integrated semiconductor sensor according to claim 1, wherein the insulating layer comprises a layer thickness d_iso between 0.1 and 50 nm, and d_iso is advantageously in a range from 0.1 to 10 nm.

6. The integrated semiconductor sensor according to claim 1, wherein the semiconducting layer comprises a layer thickness d_epi between 0.1 and 50 μ

m, and d_epi is advantageously in a range from 0.1 to 10 μ

m.

7. The integrated semiconductor sensor according to claim 1, wherein the semiconducting layer includes an epitactic semiconducting layer on the semiconductor substrate.

8. The integrated semiconductor sensor according to claim 1, wherein the semiconducting layer comprises a doping of up to 10¹⁸.

9. The integrated semiconductor sensor according to claim 1, wherein the semiconductor substrate further comprises a substrate area with a doping higher than that of the semiconducting layer, and the substrate area is in contact with the semiconducting layer.

10. The integrated semiconductor sensor according to claim 9, wherein the substrate area comprises a doping of up to 10²¹.

11. The integrated semiconductor sensor according to claim 9, wherein the semiconducting layer is n-conducting and the substrate area is p⁺-conducting or the semiconducting layer is p-conducting and the substrate area is n⁺-conducting.

12. The integrated semiconductor sensor according to claim 1, wherein the protective structure is electrically isolated from parts of the semiconductor sensor that influence a mode of operation of the semiconductor sensor.

13. The integrated semiconductor sensor according to claim 1, wherein the metal layer, the semiconducting layer and the insulating layer are formed such that a Schottky diode forms.

14. The integrated semiconductor sensor according to claim 1, wherein the metal layer, the semiconducting layer and the insulating layer are formed such that an MIS tunnel diode forms.

15. The integrated semiconductor sensor according to claim 1, wherein the metal layer, the semiconducting layer and the insulating layer are formed such that an MIS capacitance forms.

16. A use of an integrated semiconductor sensor as a protection of the semiconductor sensor from an electrostatic discharge, the integrated semiconductor sensor comprising:

a semiconductor substrate with a first and a second doped trace region and a gap between the first and second trace regions, and an insulating layer that separates the semiconductor substrate along the gap from the measuring medium to form an ion-sensitive field-effect transistor;

a semiconducting layer that is applied to the semiconductor substrate;

a metal layer; and

an insulating layer,

wherein the insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

17. A use of an integrated semiconductor sensor as a protection of the semiconductor sensor from a polarity inversion and/or disallowed operating conditions, the integrated semiconductor sensor comprising:

a semiconductor substrate with a first and a second doped trace region and a gap between the first and second trace regions, and an insulating layer that separates the semiconductor substrate along the gap from the measuring medium to form an ion-sensitive field-effect transistor;

a semiconducting layer that is applied to the semiconductor substrate;

a metal layer; and

an insulating layer,

wherein the insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.