LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE

• US 20080111236A1
• Filed: 10/31/2007
• Published: 05/15/2008
• Est. Priority Date: 09/17/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lee, Jin-Yuan, Huang, Ching-Cheng, Lin, Chuen-Jye
• Granted Patent: US 9,369,175 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/15 Structure, shape, material or disposition of the bump connectors after the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H04B 1/7113 : Determination of path profile
• CPC Class Codes: H04B 1/712 : Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Claims

1. A chip package comprising:

a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, and a copper pad exposed by an opening in said passivation layer and in said polymer layer;

a copper pillar between said semiconductor device and said first surface, wherein said copper pillar is connected to said copper pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;

a solder metal between said copper pillar and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;

an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and

a contact ball on said second surface.

2. The chip package of claim 1, wherein said polymer layer comprises polyimide.

3. The chip package of claim 1, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

4. The chip package of claim 1, wherein said solder metal has a thickness of between 10 and 100 micrometers.

5. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, and a copper pad exposed by an opening in said passivation layer and in said polymer layer;

a copper pillar between said semiconductor device and said substrate, wherein said copper pillar is connected to said copper pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;

a solder metal between said copper pillar and said substrate, wherein said solder metal is joined with said substrate; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.

6. The chip package of claim 5, wherein said polymer layer comprises polyimide.

7. The chip package of claim 5, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

8. The chip package of claim 5, wherein said solder metal has a thickness of between 10 and 100 micrometers.

9. A chip package comprising:

a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a first pad exposed by an opening in said passivation layer and in said polymer layer, and a metal interconnect on said polymer layer, wherein said metal interconnect comprises a second pad connected to said first pad, wherein the position of said second pad from a top view is different from that of said first pad;

a copper pillar between said second pad and said first surface, wherein said copper pillar is connected to said first pad through said opening and said metal interconnect, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;

a solder metal between said copper pillar and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;

an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and

a contact ball on said second surface.

10. The chip package of claim 9, wherein said polymer layer comprises polyimide.

11. The chip package of claim 9, wherein said metal interconnect comprises titanium and copper.

12. The chip package of claim 9, wherein said first pad comprises copper.

13. The chip package of claim 9, wherein said first pad comprises aluminum.

14. The chip package of claim 9, wherein said metal interconnect comprises a first metal layer comprising sputtered titanium-containing material and sputtered copper and a second metal layer comprising an electroplated metal on said first metal layer.

15. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a first pad exposed by an opening in said passivation layer and in said polymer layer, and a metal interconnect on said polymer layer, wherein said metal interconnect comprises a second pad connected to said first pad, wherein the position of said second pad from a top view is different from that of said first pad;

a copper pillar between said second pad and said substrate, wherein said copper pillar is connected to said first pad through said opening and said metal interconnect, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;

a solder metal between said copper pillar and said substrate, wherein said solder metal is joined with said substrate; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.

16. The chip package of claim 15, wherein said polymer layer comprises polyimide.

17. The chip package of claim 15, wherein said metal interconnect comprises titanium and copper.

18. The chip package of claim 15, wherein said first pad comprises copper.

19. The chip package of claim 15, wherein said first pad comprises aluminum.

20. The chip package of claim 15, wherein said metal interconnect comprises a first metal layer comprising sputtered titanium-containing material and sputtered copper and a second metal layer comprising an electroplated metal on said first metal layer.