Battery Charger Apparatus With A Digital Charge Reduction Loop

• US 20080111521A1
• Filed: 11/14/2006
• Published: 05/15/2008
• Est. Priority Date: 11/14/2006
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: So, John Sung Ko, Brown, David Alan
• Granted Patent: US 7,656,132 B2
• Time in Patent Office: Days
• US Class Current: 320/137
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H02J 2207/30 Charge provided using DC bus or data bus of a computer
• CPC Class Codes: H02J 7/00308 Overvoltage protection
• CPC Class Codes: H02J 7/00716 in response to integrated charge or discharge current
• CPC Class Codes: H02J 7/04 Regulation of charging current or voltage
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A battery charger apparatus for charging a battery, comprises a charge-current control circuit for receiving a charge-current control signal to control an amount of charge current being drawn from an input source, e.g., a USB port or a line adapter; and analog control circuit for generating an analog control signal representative of a maximum amount of charge current to be used to charge a battery; a digital charge reduction loop including a circuit for determining a charge-current adjustment signal based on a source voltage of the input source; a counter for generating a digital count value based on the charge-current adjustment signal; and a digital-to-analog converter (DAC) for generating a DAC control signal based on the digital count value of the counter, the DAC control signal being representative of a reduced amount of charge current to be used to charge the battery; and a switching mechanism for selecting one of the analog control signal or the DAC control signal based on the source voltage, the selected control signal being used as the charge-current control signal to the charge-current control circuit.

Claims

1. A battery charger apparatus for charging a battery, comprising:

a charge-current control circuit for receiving a charge-current control signal to control an amount of charge current being drawn from an input source;

an analog control circuit for generating an analog control signal representative of a maximum amount of charge current to be used to charge a battery;

a digital charge reduction loop including

a circuit for determining a charge-current adjustment signal based on a source voltage of the input source,

a counter for generating a digital count value based on the charge-current adjustment signal, and

a digital-to-analog converter (DAC) for generating a DAC control signal based on the digital count value of the counter, the DAC control signal being representative of a reduced amount of charge current to be used to charge the battery; and

a switching mechanism for selecting one of the analog control signal or the DAC control signal based on the source voltage, the selected control signal being used as the charge-current control signal to the charge-current control circuit.

2. The battery charger of claim 1, wherein the charge-current control circuit is operative to limit the charge current to the maximum charge current that the battery can handle.

3. The battery charger of claim 1, wherein the circuit for determining the charge-current adjustment signal includes

a first comparator for comparing a first voltage based on the source voltage against a reference voltage to generate a first comparator output signal, the first comparator output signal being for controlling the counter;

and

a second comparator for comparing a second voltage based on the source voltage against the reference voltage to generate a second comparator output signal, the second comparator output signal being for controlling the switching mechanism.

4. The battery charger of claim 3, wherein the counter is operative to count up when the first comparator output signal is a logical high value.

5. The battery charger of claim 4, wherein the counter is operative to down when the first comparator output signal is a logical low value.

6. The battery charger of claim 3, wherein the switching mechanism is operative to select the DAC control signal as the charge-current control signal and the counter is operative to reset to a predetermined digital value, when the second comparator output signal is a logical low value.

7. The battery charger of claim 1, wherein the switching mechanism is operative to select the analog control signal when the digital count value of the counter is at a predetermined digital value.

8. The battery charger of claim 1, wherein the digital charge reduction loop further comprises a clock oscillator for generating a clock signal, and wherein the counter is operative to modify the digital count value in coordination with the clock signal.

9. The battery charger of claim 1, wherein the circuit for determining the charge-current adjustment signal includes a comparator for comparing a first voltage based on the source voltage against a reference voltage to generate a comparator control signal, the comparator control signal being for controlling the counter and the switching mechanism.

10. The battery charger of claim 9, wherein the counter is operative to count up when the comparator control signal is a logical high value.

11. The battery charger of claim 10, wherein the counter is operative to count down when the comparator control signal is a logical low value.

12. The battery charger of claim 9, wherein the switching mechanism is operative to select the DAC control signal as the charge-current control signal and the counter is operative to reset, when the comparator control signal is a logical low value and the digital counter value is at a predetermined digital value.

13. The battery charger of claim 9, wherein the switching mechanism is operative to select the analog control signal as the charge-current control signal when the digital counter value is at a predetermined digital value.

14. The battery charger of claim 1, wherein the switching mechanism includes

an RS flip-flop for receiving a reset signal when the source voltage is below a trip threshold voltage, and for receiving a set signal when the digital count value is at a predetermined digital value, the RS flip-flop being operative to generate a RS output signal;

and

a multiplexer for selecting one of the analog control signal or the DAC control signal based on the RS output signal.

15. The battery charger of claim 1, wherein the input source is a USB port.

16. The battery charger of claim 1, wherein the input source is a line adapter.

17. A method of charging a battery, comprising:

generating a first analog control signal representative of a maximum amount of charge current to be used to charge a battery;

determining a charge-current adjustment signal based on a source voltage of an input source;

generating a digital count value based on the charge-current adjustment signal;

generating a second analog control signal based on the digital count value of the counter, the second analog control signal being representative of a reduced amount of charge current to be used to charge the battery; and

selecting based on the source voltage one of the first analog control signal or the second analog control signal to use as a charge-current control signal to a charge-current control circuit.

18. The method of claim 17, further comprising limiting the charge current to the maximum charge current that the battery can handle.

19. The method of claim 17, wherein the determining the charge-current adjustment signal includes

comparing a first voltage based on the source voltage against a reference voltage to generate a first comparator output signal, the first comparator output signal being for controlling the generating the digital count value;

and

comparing a second voltage based on the source voltage against the reference voltage to generate a second comparator output signal, the second comparator output signal being for controlling the selecting.

20. The method of claim 19, wherein the generating the digital count value includes increasing the digital count value when the first comparator output signal is a logical high value.

21. The method of claim 20, wherein the generating the digital count value includes decreasing the digital count value when the first comparator output signal is a logical low value.

22. The method of claim 19, wherein, when the second comparator output signal is a logical low value, the selecting includes selecting the DAC control signal as the charge-current control signal and further comprising resetting the digital count value to a predetermined digital value.

23. The method of claim 17, wherein the selecting includes selecting the analog control signal when the digital count value is at a predetermined digital value.

24. The method of claim 17, further comprising generating a clock signal, and wherein the selecting includes modifying the digital count value in coordination with the clock signal.

25. The method of claim 17, wherein determining the charge-current control signal includes comparing a first voltage based on the source voltage against a reference voltage to generate a comparator control signal, the comparator control signal being for controlling the generating the digital count value and the selecting.

26. The method of claim 25, wherein the generating the digital count value includes counting up when the comparator control signal is a logical high value.

27. The method of claim 26, wherein the generating the digital count value includes counting down when the comparator control signal is a logical low value.

28. The method of claim 25, wherein, when the comparator control signal is a logical low value and the digital counter value is at a predetermined digital value, the selecting includes selecting the DAC control signal as the charge-current control signal and further comprising resetting the digital count value.

29. The method of claim 25, wherein the selecting includes selecting the analog control signal as the charge-current control signal when the digital counter value is at a predetermined digital value.

30. The method of claim 17, further comprising

receiving a reset signal when the source voltage is below a trip threshold voltage;

receiving a set signal when the digital count value is at a predetermined digital value; and

generating a RS output signal based on the received signal;

wherein the selecting includes selecting one of the analog control signal or the DAC control signal based on the RS output signal.

31. The method of claim 17, wherein the input source is a USB port.

32. The method of claim 17, wherein the input source is a line adapter.

33. A digital charge reduction loop in a battery charger comprising:

a circuit for determining a charge-current adjustment signal based on a source voltage of an input source;

a counter for generating a digital count value based on the charge-current adjustment signal; and

a digital-to-analog converter (DAC) for generating a DAC control signal based on the digital count value of the counter, the DAC control signal being representative of an amount of charge current to be used to charge a battery.

34. A digital charge reduction loop in a battery charger comprising:

means for determining a charge-current adjustment signal based on a source voltage of an input source;

means for generating a digital count value based on the charge-current adjustment signal; and

means for generating an analog control signal based on the digital count value, the control signal being representative of an amount of charge current to be used to charge a battery.