Apparatus and method of setting operation mode in DLL circuit

• US 20080111600A1
• Filed: 07/05/2007
• Published: 05/15/2008
• Est. Priority Date: 11/14/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Hyun Woo, Yun, Won Joo, Park, Nak Kyu
• Granted Patent: US 7,755,403 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.

Claims

1. An apparatus for setting an operation mode in a DLL (Delay Locked Loop) circuit configured to generate a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock,

wherein during three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled based thereon.

2. The apparatus of claim 1,

wherein during three cycles of the pulse signal, when levels of the phase comparing signal are a low level, a low level, and a high level, the locking completion signal is enabled.

3. An apparatus for setting an operation mode in a DLL (Delay Locked Loop) circuit, the apparatus comprising:

a reset unit configured to control a voltage level of a first node in response to a reset signal;

a power supply unit configured to supply a voltage source to a second node in response to a locking completion signal and a pulse signal;

a first control unit configured to determine whether a level of a phase comparing signal, which is input during at least three cycles of the pulse signal, is changed, thereby controlling the voltage level of the first node;

a second control unit configured to control a voltage level of the second node in response to the phase comparing signal and the pulse signal; and

a latch unit configured to latch the voltage applied at the first node, thereby outputting the locking completion signal.

4. The apparatus according to claim 3,

wherein, when a level of the phase comparing signal is maintained at a first level during two or more cycles of the pulse signal and then is changed to a second level, the first control unit controls the voltage level of the first node to be the first level.

5. The apparatus according to claim 3,

wherein the reset unit is configured to supply a voltage source to the first node, when the reset signal is enabled.

6. The apparatus according to claim 3,

wherein the reset unit comprises:

an inverter configured to invert the reset signal to provide an output signal; and

a transistor configured to have a gate terminal receiving the output signal of the inverter, a source terminal applied with an external voltage source, and a drain terminal coupled with the first node.

7. The apparatus according to claim 4,

wherein the power supply unit is configured to supply a voltage source to the second node when the locking completion signal is disabled and the pulse signal is at a first level.

8. The apparatus according to claim 3,

wherein the power supply unit comprises:

a first transistor configured to have a drain terminal, a gate terminal receiving the locking completion signal, and a source terminal applied with the external voltage source; and

a second transistor configured to have a gate terminal receiving the pulse signal, a source terminal coupled with the drain terminal of the first transistor, and a drain terminal coupled with the second node.

9. The apparatus according to claim 3,

wherein the first control unit comprises:

a first flip-flop configured to latch the phase comparing signal according to control of the pulse signal to provide an output signal; and

a second flip-flop configured to latch the output signal of the first flip-flop according to the control of the pulse signal to provide an output signal; and

a switch configured to connect, when the output signal of the first flip-flop and the output signal of the second flip-flop are at the first level, the first node and the second node.

10. The apparatus according to claim 4,

wherein the second control unit is configured to control the voltage level of the second node to be a first level, when the phase comparing signal and the pulse signal are at a second level.

11. The apparatus according to claim 3,

wherein the second control unit comprises:

a first transistor configured to have a source terminal, a gate terminal receiving the phase comparing signal, and a drain terminal coupled with the second node; and

a second transistor configured to have a gate terminal receiving the pulse signal, a drain terminal coupled with the source terminal of the first transistor, and a source terminal coupled with a ground.

12. The apparatus according to claim 3,

wherein the latch unit is configured to invert the voltage of the first node, thereby outputting the locking completion signal, and to store the locking completion signal.

13. The apparatus according to claim 3,

wherein the latch unit comprises:

a first inverter configured to receive the voltage applied at the first node, thereby outputting the locking completion signal; and

a second inverter configured to form a latch structure with the first inverter.

14. The apparatus according to claim 3, further comprising:

an output control unit configured to compare phases of a reference clock and a feedback clock, thereby generating an output control signal,

wherein the latch unit generates, when the output control signal is enabled, the locking completion signal according to the voltage applied at the first node.

15. An apparatus for setting an operation mode in a DLL (Delay Locked Loop) circuit, the apparatus comprising:

a reset unit configured to control a voltage level of a first node in response to a reset signal;

a power supply unit configured to supply a voltage source to a second node in

response to a locking completion signal and a pulse signal;

a first control unit configured to include a first flip-flop latching a phase comparing signal according to control of the pulse signal to provide an output signal and a second flip-flop latching the output signal of the first flip-flop according to the control of the pulse signal, and to change, when a logic value of levels of the phase comparing signal input to the first flip-flop is a specific combination, the voltage level of the first node;

a second control unit configured to control the voltage level of the second node in response to the phase comparing signal and the pulse signal; and

a latch unit configured to latch the voltage level at the first node, thereby outputting the locking completion signal.

16. The apparatus according to claim 15, further comprising:

an output control unit configured to compare phases of a reference clock and a feedback clock, thereby generating an output control signal,

wherein the latch unit generates, when the output control signal is enabled, the locking completion signal according to the voltage level at the first node.

17. An apparatus for setting an operation mode in a DLL (Delay Locked Loop) circuit, the apparatus comprising:

a reset unit configured to control a voltage level of a first node in response to a reset signal;

a power supply unit configured to supply a voltage source to a second node in response to a locking completion signal and a pulse signal;

a first control unit configured to controls the voltage of the first node in response to a phase comparing signal and the pulse signal;

a second control unit configured to control the voltage level of a second node in response to the phase comparing signal and the pulse signal;

an output control unit configured to compare a phase of a reference clock and a phase of a feedback clock, thereby generating an output control signal; and

a latch unit configured to latch the voltage at the first node, thereby outputting the locking completion signal according to whether the output control signal is enabled or not.

18. The apparatus according to claim 17,

wherein the output control unit is configured to enable the output control signal when a period, during which the phases of the reference clock and the feedback clock are the same, is longer than a period, during which the phases thereof are different from each other.

19. The apparatus according to claim 17,

wherein the latch unit is configured to disable the locking completion signal when the output control signal is disabled, and to enable or disable the locking completion signal according to the voltage level of the first node when the output control signal is enabled.

20. The apparatus according to claim 17,

wherein the reset unit is configured to supply a voltage source to the first node when the reset signal is enabled.

21. The apparatus according to claim 17,

wherein the power supply unit is configured to supply the voltage source to the second node when the locking completion signal is disabled and the pulse signal does not toggle.

22. The apparatus according to claim 17,

wherein the first control unit is configured to connect the first node and the second node according to control of the phase comparing signal that is transmitted when the phase of the feedback clock is earlier than the phase of the reference clock.

23. The apparatus according to claim 17,

wherein the second control unit is configured to synchronize the voltage level of the second node with a ground level by the phase comparing signal transmitted when the phase of the reference clock is earlier than the phase of the feedback clock and the pulse signal at the time of toggling.

24. The apparatus according to claim 17,

wherein the output control unit comprises:

a same phase extracting unit configured to extract a period, during which the phases of the reference clock and the feedback clock are the same, thereby outputting a same phase signal;

a DA converting unit configured to convert the same phase signal into an analog signal; and

a comparing unit configured to compare the analog signal of the DA converting unit with a reference voltage, thereby outputting the output control signal.

25. The apparatus according to claim 24,

wherein the same phase extracting unit is configured to generate the same phase signal that has a first level during a period which the phases of the reference clock and the feedback clock are the same, and that has a second level that is obtained by inverting the first level during a period which the phases of the reference clock and the feedback clock are different from each other.

26. The apparatus according to claim 25,

wherein the DA converting unit is configured to output the analog signal that has the first level when a period, during which the level of the same phase signal is at the first level, is longer than a period, during which the level of the same phase is at the second level, and has the second level when the period, during which the level of the same phase signal is at the first level, is shorter than the period, during which the level of the same phase signal is at the second level.

27. The apparatus according to claim 26,

wherein the DA converting unit comprises:

a first switch configured to connect, when the same phase signal is at the first level, a supply terminal of an external voltage source and a third node;

a second switch configured to connect, when the same phase signal is at the second level, the third node and a ground terminal; and

a capacitor between the third node and the ground terminal.

28. The apparatus according to claim 26,

wherein the comparing unit is configured to enable the output control signal when the output signal of the DA converting unit is at the first level, and to disable the output control signal when the output signal of the DA converting unit is at the second level.

29. A method of setting an operation mode in a DLL (Delay Locked Loop) circuit, the method comprising:

controlling a voltage level of a voltage applying node in response to a phase comparing signal, a pulse signal, and a locking completion signal;

comparing a phase of a reference clock and a phase of a feedback clock, thereby generating an output control signal; and

outputting a voltage applied at the voltage applying node as the locking completion signal according to control of the output control signal.

30. The method according to claim 29,

wherein the generating the output control signal comprises enabling the output control signal when a period, during which the phases of the reference clock and the feedback clock are the same, is longer than a period, during which the phases of the reference clock and the feedback clock are different from each other, and to disable the output control signal when the period, during which the phases of the reference clock and the feedback clock are the same, is shorter than the period, during which the phases of the reference clock and the feedback clock are different from each other.

31. The method according to claim 29,

wherein the generating the output control signal comprises:

extracting a period, during which the phases of the reference clock and the feedback clock are the same, thereby outputting a same phase signal;

converting the same phase signal into an analog signal; and

comparing a level of the analog signal with a level of a reference voltage, thereby outputting the output control signal.

32. The method according to claim 31,

wherein the outputting the same phase signal comprises generating the same phase signal that has a first level during a period which the phases of the reference clock and the feedback clock are the same, and has a second level that is obtained by inverting the first level during a period which the phases of the reference clock and the feedback clock are different from each other.

33. The method according to claim 32,

wherein the converting the same phase signal into the analog signal comprises outputting the analog signal that has the first level when a period, during which the same phase signal is at the first level, is longer than a period, during which the same phase signal is at the second level, and has the second level when the period, during which the same phase signal is at the first level, is shorter than the period, during which the same phase signal is at the second level.

34. The method according to claim 31,

wherein the outputting of the output control signal comprises enabling the output control signal, when the level of the analog signal is higher than the level of the reference voltage, and to disable the output control signal, when the level of the analog signal is lower than the level of the reference voltage.